Refer to the PDF data sheet for device specific package drawings
A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two modes of Common Refclk Rx Architecture are supported:
In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs. Alternatively, an LVDS clock source can be used with the following additional requirements:
In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External near-side termination to ground described in Table 8-26 is required on both of the ljcb_clkn / ljcb_clkp outputs in this mode.
|ljcb_clkn / ljcb_clkp AC coupling capacitor value||100||nF|
|ljcb_clkn / ljcb_clkp AC coupling capacitor package size||0402||0603||EIA(1)(2)|
|ljcb_clkn / ljcb_clkp near-side termination to ground value||47.5||50||52.5||Ω|