SPRS950F December 2015 – May 2019 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
Refer to the PDF data sheet for device specific package drawings
TI only supports board designs that follow the guidelines outlined in this document. The switching characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-30 and Figure 8-49.
|DDR21||tc(DDR_CLK)||Cycle time, DDR_CLK||2.5||8||ns|