Refer to the PDF data sheet for device specific package drawings
The Imaging Processor Unit (IPU) subsystem contains two Arm® Cortex™-M4 cores (IPU_C0 and IPU_C1) that share a common level 1 (L1) cache (called unicache). The two Cortex-M4 cores are completely homogeneous to one another. Any task possible using one Cortex-M4 core is also possible using the other Cortex-M4 core. Both Cortex-M4 cores could be used for tasks such as running RTOS, controlling ISP, SIMCOP, DSS, and other functions. It is software responsibility to distribute the various tasks between the Cortex-M4 cores for optimal performance. The integrated interrupt handling of the IPU subsystem allows it to function as an efficient control unit.
For more information, see Dual Cortex-M4 IPU Subsystem section in the device TRM.