SPRS975H August 2016 – February 2020 DRA780 , DRA781 , DRA782 , DRA783 , DRA785 , DRA786 , DRA787 , DRA788
Refer to the PDF data sheet for device specific package drawings
For more information, see the Quad Serial Peripheral Interface section in the device TRM.
The IO timings provided in Section 5.9, Timing Requirements and Switching Characteristics are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-49.
|qspi1_sclk||QSPI1 Serial Clock||O||C8|
|qspi1_rtclk||QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer to PCB Guidelines for QSPI1||I||B7,C14,D8,F13|
|qspi1_d0||QSPI1 Data. This pin is output data for all commands/writes and for dual read and quad read modes it becomes input data pin during read phase.||IO||B9|
|qspi1_d1||QSPI1 Data. Input read data in all modes.||IO||F10|
|qspi1_d2||QSPI1 Data. This pin is used only in quad read mode as input data pin during read phase||IO||A9|
|qspi1_d3||QSPI1 Data. This pin is used only in quad read mode as input data pin during read phase||IO||D10|
|qspi1_cs0||QSPI1 Chip Select. This pin is used for QSPI1 boot modes.||IO||E10|
|qspi1_cs1||QSPI1 Chip Select||IO||F15|