Refer to the PDF data sheet for device specific package drawings
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock, CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through an asynchronous multplexing.
For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.
|DPLL NAME||CONTROLLED BY PRCM|
Table 5-25 and summarize the DPLL characteristics and assume testing over recommended operating conditions.
|finput||CLKINP input frequency||0.032||52||MHz||FINP|
|finternal||Internal reference frequency||0.15||52||MHz||REFCLK|
|fCLKINPHIF||CLKINPHIF input frequency||10||1400||MHz||FINPHIF|
|fCLKINPULOW||CLKINPULOW input frequency||0.001||600||MHz||Bypass mode: fCLKOUT = fCLKINPULOW / (M1 + 1) if ulowclken = 1(7)|
|fCLKOUT||CLKOUT output frequency||20(1)||1800(3)||MHz||[M / (N + 1)] × FINP × [1 / M2] (in locked condition)|
|fCLKOUTx2||CLKOUTx2 output frequency||40(1)||2200(3)||MHz||2 × [M / (N + 1)] × FINP × [1 / M2] (in locked condition)|
|fCLKOUTHIF||CLKOUTHIF output frequency||20(4)||1400(5)||MHz||FINPHIF / M3 if clkinphifsel = 1|
|40(4)||2200(5)||MHz||2 × [M / (N + 1)] × FINP × [1 / M3] if clkinphifsel = 0|
|fCLKDCOLDO||DCOCLKLDO output frequency||40||2800||MHz||2 × [M / (N + 1)] × FINP (in locked condition)|
|tlock||Frequency lock time||6 + 350 × REFCLK||µs|
|plock||Phase lock time||6 + 500 × REFCLK||µs|
|trelock-L||Relock time—Frequency lock(6) (LP relock time from bypass)||6 + 70 × REFCLK||µs||DPLL in LP relock time: lowcurrstdby = 1|
|prelock-L||Relock time—Phase lock(6) (LP relock time from bypass)||6 + 120 × REFCLK||µs||DPLL in LP relock time: lowcurrstdby = 1|
|trelock-F||Relock time—Frequency lock(6) (fast relock time from bypass)||3.55 + 70 × REFCLK||µs||DPLL in fast relock time: lowcurrstdby = 0|
|prelock-F||Relock time—Phase lock(6) (fast relock time from bypass)||3.55 + 120 × REFCLK||µs||DPLL in fast relock time: lowcurrstdby = 0|
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.