7.3.1 General Constraints and Theory
- Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using TI recommended PMICs without remote sensing as measured from PMIC’s power inductor and filter capacitor node to Processor input including any ground return losses.
- Max PCB static/DC voltage drop (IRd) budget can be relaxed to 7.5% of supply voltage when using PMICs with remote sensing at the load as measured from PMIC’s power inductor and filter capacitor node to Device’s supply input including any ground return losses.
- PMIC component DM and guidelines should be referenced for the following:
- Routing remote feedback sensing to optimize per each SMPS’s implementation
- Selecting power filtering capacitor values and PCB placement.
- Max Effective Resistance (Reff) budget can range from 4 – 100mΩ for key Device power rails not including ground returns depending upon maximum load currents and maximum DC voltage drop budget (as discussed above).
- Max Device supply input voltage difference budget of 5mV under max current loading shall be maintained across all balls connected to a common power rail. This represents any voltage difference that may exist between a remote sense point to any power input.
- Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high frequency decoupling capacitors including ground returns should range from 0.4 – 2.5nH depending upon maximum transient load currents.
- Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device including ground returns are as follows:
- +/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~ 200kHz)
- +/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)
- Max PCB Impedance (Z) vs Frequency (F) budget between Device’s power inputs and PMIC’s output power filter node including ground return is determined by applying the Frequency Domain Target Impedance Method to determine the PCB’s maximum frequency of interest (Fpcb). Ideally a properly designed and decoupled PDN will exhibit smoothly increasing Z vs. F curve. There are 2 general regions of interest as can be seen in Figure 7-14.
- 1st area is from DC (0Hz) up to Fpmic (typ a few 100 kHz) where a PMIC’s transient response characteristic (i.e. Switching Freq, Compensation Loop BW) dominate. A PDN’s Z is typically very low due to power filtering & bulk capacitor values when PDN has very low trace resistance (i.e. good Reff performance). The goal is to maintain a smoothly increasing Z that is less than Zt1 over this low frequency range. This will ensure that a max transient current event will not cause a voltage drop more than the PMIC’s current step response can support (typ 3%).
- 2nd area is from Fpmic up to Fpcb (typ 20-100MHz) where a PCB’s inherent characteristics (i.e. parasitic capacitance, planar spreading inductances) dominate. A PDN’s Z will naturally increase with frequency. At frequencies between Fpmic up to Fpcb, the goal is to maintain a smoothly increasing Z to be less than Zt2. This will ensue that the high frequency content of a max transient current event will not cause a voltage drop to be more than 5% of the min supply voltage.
Figure 7-14 PDN’s Target impedance
1.Voltage Rail Drop includes regulation accuracy, voltage distribution drops, and all dynamic events such as transient noise, AC ripple, voltage dips etc.
2.Typical max transient current is defined as 50% of max current draw possible.