SPRSP57E april   2020  – june 2023 DRA821U , DRA821U-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
        2. 6.3.2.2 DDRSS Mapping
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
        2. 6.3.9.2 MAIN Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW5G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MAIN Domain
        2. 6.3.21.2 MCU Domain
      22. 6.3.22 MCASP
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 DMTIMER
        1. 6.3.23.1 MAIN Domain
        2. 6.3.23.2 MCU Domain
      24. 6.3.24 Emulation and Debug
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 System and Miscellaneous
        1. 6.3.25.1 Boot Mode Configuration
          1. 6.3.25.1.1 MAIN Domain
          2. 6.3.25.1.2 MCU Domain
        2. 6.3.25.2 Clock
          1. 6.3.25.2.1 MAIN Domain
          2. 6.3.25.2.2 WKUP Domain
        3. 6.3.25.3 System
          1. 6.3.25.3.1 MAIN Domain
          2. 6.3.25.3.2 WKUP Domain
          3. 6.3.25.3.3 VMON
        4. 6.3.25.4 EFUSE
      26. 6.3.26 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Power-On-Hours (POH)
    5. 7.5 Operating Performance Points
    6. 7.6 Electrical Characteristics
      1. 7.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.6.3  HFOSC Electrical Characteristics
      4. 7.6.4  eMMCPHY Electrical Characteristics
      5. 7.6.5  SDIO Electrical Characteristics
      6. 7.6.6  ADC12BT Electrical Characteristics
      7. 7.6.7  LVCMOS Electrical Characteristics
      8. 7.6.8  USB2PHY Electrical Characteristics
      9. 7.6.9  SERDES Electrical Characteristics
      10. 7.6.10 DDR Electrical Characteristics
    7. 7.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.7.2 Hardware Requirements
      3. 7.7.3 Programming Sequence
      4. 7.7.4 Impact to Your Hardware Warranty
    8. 7.8 Thermal Resistance Characteristics
      1. 7.8.1 Thermal Resistance Characteristics
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameters and Information
      2. 7.9.2 Power Supply Sequencing
        1. 7.9.2.1 Power Supply Slew Rate Requirement
        2. 7.9.2.2 Combined MCU and Main Domains Power- Up Sequencing
        3. 7.9.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.9.2.4 Independent MCU and Main Domains Power- Up Sequencing
        5. 7.9.2.5 Independent MCU and Main Domains Power- Down Sequencing
        6. 7.9.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        7. 7.9.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        8. 7.9.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 7.9.3 System Timing
        1. 7.9.3.1 Reset Timing
        2. 7.9.3.2 Safety Signal Timing
        3. 7.9.3.3 Clock Timing
      4. 7.9.4 Clock Specifications
        1. 7.9.4.1 Input Clocks / Oscillators
          1. 7.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.9.4.1.1.1 Load Capacitance
            2. 7.9.4.1.1.2 Shunt Capacitance
          2. 7.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.9.4.1.3.1 Load Capacitance
            2. 7.9.4.1.3.2 Shunt Capacitance
          4. 7.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.9.4.1.5 Auxiliary OSC1 Not Used
          6. 7.9.4.1.6 WKUP_LF_CLKIN Internal Oscillator Clock Source
          7. 7.9.4.1.7 WKUP_LF_CLKIN Not Used
        2. 7.9.4.2 Output Clocks
        3. 7.9.4.3 PLLs
        4. 7.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 7.9.4.5 Interface Clock Specifications
          1. 7.9.4.5.1 Interface Clock Terminology
          2. 7.9.4.5.2 Interface Clock Frequency
      5. 7.9.5 Peripherals
        1. 7.9.5.1  ATL
          1. 7.9.5.1.1 ATL_PCLK Timing Requirements
          2. 7.9.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.9.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.9.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.9.5.2  CPSW2G
          1. 7.9.5.2.1 CPSW2G RMII Timings
            1. 7.9.5.2.1.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.9.5.2.1.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.9.5.2.1.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          2. 7.9.5.2.2 CPSW2G RGMII Timings
            1. 7.9.5.2.2.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.9.5.2.2.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.9.5.2.2.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.9.5.2.2.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        3. 7.9.5.3  CPSW5G
          1. 7.9.5.3.1 CPSW5G MDIO Interface Timings
          2. 7.9.5.3.2 CPSW5G RMII Timings
            1. 7.9.5.3.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.9.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.9.5.3.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 7.9.5.3.3 CPSW5G RGMII Timings
            1. 7.9.5.3.3.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.9.5.3.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.9.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.9.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        4. 7.9.5.4  DDRSS
        5. 7.9.5.5  ECAP
          1. 7.9.5.5.1 Timing Requirements for ECAP
          2. 7.9.5.5.2 Switching Characteristics for ECAP
        6. 7.9.5.6  EPWM
          1. 7.9.5.6.1 Timing Requirements for EPWM
          2. 7.9.5.6.2 Switching Characteristics for EPWM
        7. 7.9.5.7  EQEP
          1. 7.9.5.7.1 Timing Requirements for EQEP
          2. 7.9.5.7.2 Switching Characteristics for EQEP
        8. 7.9.5.8  GPIO
        9. 7.9.5.9  GPMC
          1. 7.9.5.9.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.9.5.9.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.9.5.9.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.9.5.9.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.9.5.9.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.9.5.9.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.9.5.9.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.9.5.9.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.9.5.9.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        10. 7.9.5.10 HyperBus
          1. 7.9.5.10.1 Timing Requirements for HyperBus Initialization
          2. 7.9.5.10.2 HyperBus 166 MHz Switching Characteristics
          3. 7.9.5.10.3 HyperBus 100 MHz Switching Characteristics
        11. 7.9.5.11 I2C
        12. 7.9.5.12 I3C
        13. 7.9.5.13 MCAN
        14. 7.9.5.14 MCASP
          1. 7.9.5.14.1 Timing Requirements for MCASP
        15. 7.9.5.15 MCSPI
          1. 7.9.5.15.1 MCSPI — Controller Mode
          2. 7.9.5.15.2 MCSPI — Peripheral Mode
        16. 7.9.5.16 eMMC/SD/SDIO
          1. 7.9.5.16.1 MMCSD0 - eMMC Interface
            1. 7.9.5.16.1.1 Legacy SDR Mode
            2. 7.9.5.16.1.2 High Speed SDR Mode
            3. 7.9.5.16.1.3 High Speed DDR Mode
            4. 7.9.5.16.1.4 HS200 Mode
            5. 7.9.5.16.1.5 HS400 Mode
          2. 7.9.5.16.2 MMCSDi — MMCSD1 — SD/SDIO Interface
            1. 7.9.5.16.2.1 Default speed Mode
            2. 7.9.5.16.2.2 High Speed Mode
            3. 7.9.5.16.2.3 UHS–I SDR12 Mode
            4. 7.9.5.16.2.4 UHS–I SDR25 Mode
            5. 7.9.5.16.2.5 UHS–I SDR50 Mode
            6. 7.9.5.16.2.6 UHS–I DDR50 Mode
            7. 7.9.5.16.2.7 UHS–I SDR104 Mode
        17. 7.9.5.17 NAVSS
          1. 7.9.5.17.1 Timing Requirements for CPTS Input
          2. 7.9.5.17.2 Switching Characteristics for CPTS Output
        18. 7.9.5.18 OSPI
          1. 7.9.5.18.1 OSPI With Data Training
            1. 7.9.5.18.1.1 OSPI Switching Characteristics – Data Training
          2. 7.9.5.18.2 OSPI Without Data Training
            1. 7.9.5.18.2.1 OSPI Switching Characteristics – DDR Mode
            2. 7.9.5.18.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.9.5.18.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.9.5.18.2.4 OSPI Timing Requirements – SDR Mode
        19. 7.9.5.19 PCIE
        20. 7.9.5.20 Timers
          1. 7.9.5.20.1 Timing Requirements for Timers
          2. 7.9.5.20.2 Switching Characteristics for Timers
        21. 7.9.5.21 UART
          1. 7.9.5.21.1 UART Timing Requirements
          2. 7.9.5.21.2 UART Switching Characteristics
        22. 7.9.5.22 USB
      6. 7.9.6 Emulation and Debug
        1. 7.9.6.1 Debug Trace
        2. 7.9.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
          1. 7.9.6.2.1 JTAG Electrical Data and Timing
            1. 7.9.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG
            2. 7.9.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
    3. 8.3 Other Subsystems
      1. 8.3.1 MSMC
      2. 8.3.2 NAVSS
        1. 8.3.2.1 NAVSS0
        2. 8.3.2.2 MCU_NAVSS
      3. 8.3.3 PDMA Controller
      4. 8.3.4 Peripherals
        1. 8.3.4.1  ADC
        2. 8.3.4.2  ATL
        3. 8.3.4.3  CPSW2G
        4. 8.3.4.4  CPSW5G
        5. 8.3.4.5  DCC
        6. 8.3.4.6  DDRSS
        7. 8.3.4.7  ECAP
        8. 8.3.4.8  EPWM
        9. 8.3.4.9  ELM
        10. 8.3.4.10 ESM
        11. 8.3.4.11 EQEP
        12. 8.3.4.12 GPIO
        13. 8.3.4.13 GPMC
        14. 8.3.4.14 Hyperbus
        15. 8.3.4.15 I2C
        16. 8.3.4.16 I3C
        17. 8.3.4.17 MCAN
        18. 8.3.4.18 MCASP
        19. 8.3.4.19 MCRC Controller
        20. 8.3.4.20 MCSPI
        21. 8.3.4.21 MMC/SD
        22. 8.3.4.22 OSPI
        23. 8.3.4.23 PCIE
        24. 8.3.4.24 SerDes
        25. 8.3.4.25 WWDT
        26. 8.3.4.26 Timers
        27. 8.3.4.27 UART
        28. 8.3.4.28 USB
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 USB VBUS Design Guidelines
      4. 9.3.4 System Power Supply Monitor Design Guidelines
      5. 9.3.5 High Speed Differential Signal Routing Guidance
      6. 9.3.6 Thermal Solution Guidance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALM|433
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

Table 6-1 Pin Attributes
BALL NUMBER
[1]		 BALL
NAME
[2]		 SIGNAL
NAME
[3]		 MUX
MODE
[4]		 TYPE
[5]		 BALL RESET STATE
[6]		 BALL RESET REL. MUX
MODE
[7]		 I/O
VOLTAGE
VALUE
[8]		 POWER
[9]		 HYS
[10]		 BUFFER
TYPE
[11]		 PULL
UP/DOWN
TYPE
[12]		 DSIS
[13]		 RX
ACTIVE/
TX
DISABLE
[14]		 IO
RET
[15]
M7 CAP_VDDS0 CAP_VDDS0 PWR
G14 CAP_VDDS0_MCU CAP_VDDS0_MCU PWR
F9 CAP_VDDS1_MCU CAP_VDDS1_MCU PWR
T12 CAP_VDDS2 CAP_VDDS2 PWR
F10 CAP_VDDS2_MCU CAP_VDDS2_MCU PWR
L15 CAP_VDDS5 CAP_VDDS5 PWR
H1 DDR0_CKN DDR0_CKN IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
G1 DDR0_CKP DDR0_CKP IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
J5 DDR0_RESETn DDR0_RESETn IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
G4 DDR0_CA0 DDR0_CA0 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
H3 DDR0_CA1 DDR0_CA1 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
J4 DDR0_CA2 DDR0_CA2 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
K1 DDR0_CA3 DDR0_CA3 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
J2 DDR0_CA4 DDR0_CA4 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
H5 DDR0_CA5 DDR0_CA5 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
K5 DDR0_CAL0 DDR0_CAL0 A 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDRCALR
G2 DDR0_CKE0 DDR0_CKE0 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
H2 DDR0_CKE1 DDR0_CKE1 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
G3 DDR0_CSn0_0 DDR0_CSn0_0 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
K2 DDR0_CSn0_1 DDR0_CSn0_1 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
G5 DDR0_CSn1_0 DDR0_CSn1_0 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
J3 DDR0_CSn1_1 DDR0_CSn1_1 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
A3 DDR0_DM0 DDR0_DM0 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
E4 DDR0_DM1 DDR0_DM1 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
N1 DDR0_DM2 DDR0_DM2 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
R4 DDR0_DM3 DDR0_DM3 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
B4 DDR0_DQ0 DDR0_DQ0 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
A4 DDR0_DQ1 DDR0_DQ1 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
C4 DDR0_DQ2 DDR0_DQ2 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
C1 DDR0_DQ3 DDR0_DQ3 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
C3 DDR0_DQ4 DDR0_DQ4 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
C2 DDR0_DQ5 DDR0_DQ5 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
A2 DDR0_DQ6 DDR0_DQ6 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
B3 DDR0_DQ7 DDR0_DQ7 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
D1 DDR0_DQ8 DDR0_DQ8 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
D2 DDR0_DQ9 DDR0_DQ9 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
F2 DDR0_DQ10 DDR0_DQ10 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
E3 DDR0_DQ11 DDR0_DQ11 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
F3 DDR0_DQ12 DDR0_DQ12 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
F4 DDR0_DQ13 DDR0_DQ13 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
D4 DDR0_DQ14 DDR0_DQ14 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
F5 DDR0_DQ15 DDR0_DQ15 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
K4 DDR0_DQ16 DDR0_DQ16 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
L4 DDR0_DQ17 DDR0_DQ17 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
M4 DDR0_DQ18 DDR0_DQ18 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
L3 DDR0_DQ19 DDR0_DQ19 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
L2 DDR0_DQ20 DDR0_DQ20 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
L1 DDR0_DQ21 DDR0_DQ21 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
M3 DDR0_DQ22 DDR0_DQ22 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
N2 DDR0_DQ23 DDR0_DQ23 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
R3 DDR0_DQ24 DDR0_DQ24 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
T1 DDR0_DQ25 DDR0_DQ25 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
P1 DDR0_DQ26 DDR0_DQ26 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
P2 DDR0_DQ27 DDR0_DQ27 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
N4 DDR0_DQ28 DDR0_DQ28 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
P3 DDR0_DQ29 DDR0_DQ29 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
P4 DDR0_DQ30 DDR0_DQ30 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
N5 DDR0_DQ31 DDR0_DQ31 IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
B1 DDR0_DQS0N DDR0_DQS0N IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
B2 DDR0_DQS0P DDR0_DQS0P IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
E1 DDR0_DQS1N DDR0_DQS1N IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
E2 DDR0_DQS1P DDR0_DQS1P IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
M1 DDR0_DQS2N DDR0_DQS2N IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
M2 DDR0_DQS2P DDR0_DQS2P IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
R1 DDR0_DQS3N DDR0_DQS3N IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
R2 DDR0_DQS3P DDR0_DQS3P IO 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
R5 DDR_RET DDR_RET I 1.1 V VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS DDR
U3 ECAP0_IN_APWM_OUT ECAP0_IN_APWM_OUT 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0
SYNC0_OUT 1 O
CPTS0_RFT_CLK 2 I I
I2C1_SCL 3 IOD 1
CPTS0_HW1TSPUSH 4 I 0
UART3_RXD 5 I 1
SPI7_CS0 6 IO 1
GPIO0_58 7 IO pad
A13 EMU0 EMU0 0 IO OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
D12 EMU1 EMU1 0 IO OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0/0
U6 EXTINTn EXTINTn 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1
GPIO0_0 7 IO pad
T3 EXT_REFCLK1 EXT_REFCLK1 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0
SYNC1_OUT 1 O
I2C1_SDA 3 IOD 1
CPTS0_HW2TSPUSH 4 I 0
UART3_TXD 5 O
SPI7_CLK 6 IO 0
GPIO0_59 7 IO pad
U12 GPIO0_41 RGMII2_TX_CTL 4 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD Yes
RMII2_TXD0 5 O
GPIO0_41 7 IO pad
SPI6_D1 8 IO 0
UART4_RXD 11 I 1
MCASP2_ACLKX 12 IO 0
GPMC0_A13 13 OZ
U13 GPMC0_CLK GPMC0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 Yes
USB0_DRVVBUS 1 O
RGMII4_RD3 4 I 0
GPIO0_44 7 IO pad
SPI0_CS3 10 IO 1
UART9_RXD 11 I 1
V3 I2C0_SCL I2C0_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1
GPIO0_56 7 IO pad
W2 I2C0_SDA I2C0_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1
GPIO0_57 7 IO pad
V20 MCAN0_RX MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII4_RD1 4 I 0
MCAN0_RX 6 I 1
GPIO0_10 7 IO pad
EQEP2_S 9 IO 0
GPMC0_A2 11 OZ
MCASP0_AXR10 12 IO 0
V18 MCAN0_TX MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII4_RD0 4 I 0
MCAN0_TX 6 O
GPIO0_9 7 IO pad
EQEP2_B 9 I 0
GPMC0_A1 11 OZ
MCASP0_AXR9 12 IO 0
AUDIO_EXT_REFCLK0 14 IO 0
V16 MCAN1_RX MCAN1_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII4_RD2 4 I 0
RMII2_TXD1 5 O
MCAN1_RX 6 I 1
GPIO0_12 7 IO pad
SPI6_CS1 8 IO 1
EQEP2_I 9 IO 0
GPMC0_AD7 10 IO 0
UART6_CTSn 11 I 1
MCASP0_AXR12 12 IO 0
OBSCLK1 14 O
W21 MCAN1_TX MCAN1_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII2_TXC 4 O
RMII2_TX_EN 5 O
MCAN1_TX 6 O
GPIO0_11 7 IO pad
SPI6_CS0 8 IO 1
EHRPWM_SOCA 9 O
GPMC0_A3 11 OZ
MCASP0_AXR11 12 IO 0
Y19 MCAN2_RX MCAN2_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII1_TD1 4 O
RMII4_RXD1 5 I 0
MCAN2_RX 6 I 1
GPIO0_14 7 IO pad
SPI5_CS2 8 IO 1
EHRPWM0_B 9 IO 0
TRC_DATA2 10 O
UART3_TXD 11 O
MCASP1_ACLKX 12 IO 0
UART9_RTSn 13 O
GPMC0_AD9 14 IO 0
Y18 MCAN2_TX MCAN2_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII1_TD0 4 O
RMII4_RXD0 5 I 0
MCAN2_TX 6 O
GPIO0_13 7 IO pad
SPI5_CS3 8 IO 1
EHRPWM1_A 9 IO 1
TRC_DATA3 10 O
UART3_RXD 11 I 1
MCASP1_AFSX 12 IO 0
UART9_CTSn 13 I 1
GPMC0_AD8 14 IO 0
W16 MCAN3_RX MCAN3_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII1_TD3 4 O
RMII4_RX_ER 5 I 0
MCAN3_RX 6 I 1
GPIO0_16 7 IO pad
SPI5_CS0 8 IO 1
EHRPWM_TZn_IN0 9 I 0
TRC_DATA0 10 O
GPMC0_A4 11 OZ
MCASP0_AXR0 12 IO 0
SYNC2_OUT 14 O
Y21 MCAN3_TX MCAN3_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII1_TD2 4 O
RMII4_CRS_DV 5 I 0
MCAN3_TX 6 O
GPIO0_15 7 IO pad
SPI5_D0 8 IO 0
EHRPWM0_A 9 IO 0
TRC_DATA1 10 O
MCASP0_AXR1 12 IO 0
GPMC0_AD10 14 IO 0
Y20 MCAN4_RX MCAN4_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII1_TXC 4 O
RMII4_TX_EN 5 O
MCAN4_RX 6 I 1
GPIO0_18 7 IO pad
SPI5_D1 8 IO 0
EHRPWM1_B 9 IO 0
TRC_DATA4 10 O
I2C2_SDA 11 IOD 1
MCASP0_AXR2 12 IO 0
GPMC0_AD12 14 IO 0
W15 MCAN4_TX MCAN4_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII1_TX_CTL 4 O
RMII4_TXD0 5 O
MCAN4_TX 6 O
GPIO0_17 7 IO pad
SPI5_CLK 8 IO 0
EHRPWM0_SYNCI 9 I 0
TRC_CLK 10 O
I2C2_SCL 11 IOD 1
MCASP0_ACLKX 12 IO 0
GPMC0_AD11 14 IO 0
V19 MCAN5_RX MCAN5_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII3_RD0 4 I 0
RMII3_RXD0 5 I 0
MCAN5_RX 6 I 1
GPIO0_20 7 IO pad
I2C3_SCL 8 IOD 1
EHRPWM_TZn_IN5 9 I 0
TRC_DATA21 10 O
GPMC0_A5 11 OZ
MCASP1_AXR7 12 IO 0
V21 MCAN5_TX MCAN5_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII3_RXC 4 I 0
RMII4_TXD1 5 O
MCAN5_TX 6 O
GPIO0_19 7 IO pad
SPI5_CS1 8 IO 1
EHRPWM4_B 9 IO 0
TRC_DATA17 10 O
UART6_RTSn 11 O
MCASP0_AXR7 12 IO 0
GPMC0_DIR 13 O
SYNC3_OUT 14 O
U14 MCAN6_RX MCAN6_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII3_RD2 4 I 0
RMII3_CRS_DV 5 I 0
MCAN6_RX 6 I 1
GPIO0_22 7 IO pad
EHRPWM5_A 9 IO 0
TRC_DATA19 10 O
MCASP1_AXR5 12 IO 0
GPMC0_AD13 14 IO 0
T13 MCAN6_TX MCAN6_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII3_RD1 4 I 0
RMII3_RXD1 5 I 0
MCAN6_TX 6 O
GPIO0_21 7 IO pad
I2C3_SDA 8 IOD 1
EHRPWM5_B 9 IO 0
TRC_DATA20 10 O
GPMC0_A6 11 OZ
MCASP1_AXR6 12 IO 0
U15 MCAN7_RX MCAN7_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII3_RX_CTL 4 I 0
RMII3_TXD0 5 O
MCAN7_RX 6 I 1
GPIO0_24 7 IO pad
SPI3_CS1 8 IO 1
EHRPWM3_A 9 IO 0
TRC_DATA11 10 O
MCASP0_AFSR 12 IO 0
GPMC0_AD15 14 IO 0
U16 MCAN7_TX MCAN7_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII3_RD3 4 I 0
RMII3_RX_ER 5 I 0
MCAN7_TX 6 O
GPIO0_23 7 IO pad
SPI3_CS0 8 IO 1
EHRPWM_TZn_IN4 9 I 0
TRC_DATA18 10 O
MCASP1_AXR4 12 IO 0
GPMC0_AD14 14 IO 0
U19 MCAN8_RX MCAN8_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII3_TD1 4 O
RMII3_TXD1 5 O
MCAN8_RX 6 I 1
GPIO0_26 7 IO pad
SPI3_CS3 8 IO 1
EHRPWM3_SYNCO 9 O
TRC_DATA14 10 O
UART3_RTSn 11 O
MCASP0_AXR4 12 IO 0
GPMC0_A8 13 OZ
UART0_DSRn 14 I 1
T15 MCAN8_TX MCAN8_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
GPMC0_A7 3 OZ
RGMII3_TD0 4 O
RMII3_TX_EN 5 O
MCAN8_TX 6 O
GPIO0_25 7 IO pad
SPI3_CS2 8 IO 1
EHRPWM_TZn_IN3 9 I 0
TRC_DATA15 10 O
UART3_CTSn 11 I 1
MCASP0_AXR5 12 IO 0
UART0_DCDn 14 I 1
U18 MCAN9_RX MCAN9_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII3_TD3 4 O
MCAN9_RX 6 I 1
GPIO0_28 7 IO pad
SPI3_D0 8 IO 0
EHRPWM3_B 9 IO 0
TRC_DATA12 10 O
MCASP1_ACLKR 12 IO 0
GPMC0_A10 13 OZ
MCASP1_AXR11 14 IO 0
T14 MCAN9_TX MCAN9_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII3_TD2 4 O
MCAN9_TX 6 O
GPIO0_27 7 IO pad
SPI3_CLK 8 IO 0
EHRPWM3_SYNCI 9 I 0
TRC_DATA13 10 O
MCASP1_AFSR 12 IO 0
GPMC0_A9 13 OZ
MCASP1_AXR10 14 IO 0
U20 MCAN10_RX MCAN10_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII3_TXC 4 O
MCAN10_RX 6 I 1
GPIO0_30 7 IO pad
SPI2_CLK 8 IO 1
EHRPWM4_A 9 IO 0
TRC_DATA16 10 O
UART2_RTSn 11 O
MCASP0_AXR6 12 IO 0
GPMC0_BE0n_CLE 13 O
GPMC0_A16 14 OZ
U17 MCAN10_TX MCAN10_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII3_TX_CTL 4 O
MCAN10_TX 6 O
GPIO0_29 7 IO pad
SPI3_D1 8 IO 0
EHRPWM_SOCB 9 O
TRC_DATA10 10 O
UART2_CTSn 11 I 1
MCASP0_ACLKR 12 IO 0
GPMC0_WAIT1 13 I 0
GPMC0_A22 14 OZ
Y13 MCAN11_RX MCAN11_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII2_RD0 4 I 0
MCAN11_RX 6 I 1
GPIO0_32 7 IO pad
SPI2_CS1 8 IO 1
EQEP0_B 9 I 0
UART3_TXD 11 O
MCASP0_AXR14 12 IO 0
GPMC0_A12 13 OZ
UART0_RIn 14 I 1
Y14 MCAN11_TX MCAN11_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII2_RXC 4 I 0
MCAN11_TX 6 O
GPIO0_31 7 IO pad
SPI2_CS0 8 IO 1
EQEP0_A 9 I 0
SPI0_CS2 10 IO 1
UART3_RXD 11 I 1
MCASP0_AXR13 12 IO 0
GPMC0_A11 13 OZ
UART0_DTRn 14 O
AA14 MCAN12_RX MCAN12_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII2_RD2 4 I 0
MCAN12_RX 6 I 1
GPIO0_34 7 IO pad
SPI2_CS3 8 IO 1
EQEP1_B 9 I 0
I2C6_SDA 10 IOD 1
UART2_TXD 11 O
MCASP1_AXR8 12 IO 0
I3C0_SDAPULLEN 13 OD
GPMC0_A18 14 OZ
AA15 MCAN12_TX MCAN12_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII2_RD1 4 I 0
MCAN12_TX 6 O
GPIO0_33 7 IO pad
SPI2_CS2 8 IO 1
EQEP1_A 9 I 0
I2C6_SCL 10 IOD 1
UART2_RXD 11 I 1
MCASP0_AXR15 12 IO 0
GPMC0_BE1n 13 O
GPMC0_A17 14 OZ
AA16 MCAN13_RX MCAN13_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII2_RX_CTL 4 I 0
GPMC0_CSn3 5 O
MCAN13_RX 6 I 1
GPIO0_36 7 IO pad
SPI2_D1 8 IO 0
EQEP0_I 9 IO 0
I2C5_SDA 10 IOD 1
UART8_RTSn 11 O
MCASP2_AXR0 12 IO 0
I3C0_SDA 13 IO 1
GPMC0_A20 14 OZ
AA18 MCAN13_TX MCAN13_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII2_RD3 4 I 0
GPMC0_WPn 5 O
MCAN13_TX 6 O
GPIO0_35 7 IO pad
SPI2_D0 8 IO 0
EQEP0_S 9 IO 0
I2C5_SCL 10 IOD 1
UART8_CTSn 11 I 1
MCASP1_AXR9 12 IO 0
I3C0_SCL 13 IO 1
GPMC0_A19 14 OZ
W20 MCAN15_RX MCAN15_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
RGMII2_TD1 4 O
RMII2_RXD1 5 I 0
GPIO0_38 7 IO pad
SPI6_CS3 8 IO 1
EQEP1_I 9 IO 0
MCAN15_RX 10 I 1
MCASP2_AXR2 12 IO 0
GPMC0_A15 13 OZ
GPMC0_ADVn_ALE 14 O
W17 MCAN15_TX MCAN15_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII2_TD0 4 O
RMII2_RXD0 5 I 0
GPIO0_37 7 IO pad
SPI6_CS2 8 IO 1
EQEP1_S 9 IO 0
MCAN15_TX 10 O
GPMC0_CSn2 11 O
MCASP2_AXR1 12 IO 0
GPMC0_A0 13 OZ
GPMC0_A21 14 OZ
U21 MCAN16_RX MCAN16_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 1/0 Yes
CLKOUT 1 OZ
RGMII4_TD0 4 O
GPIO0_46 7 IO pad
UART7_RXD 12 I 1
GPMC0_CSn1 13 O
AUDIO_EXT_REFCLK1 14 IO 0
V15 MCAN16_TX MCAN16_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RMII_REF_CLK 1 I 0
RGMII4_RX_CTL 4 I 0
GPIO0_45 7 IO pad
UART7_TXD 12 O
GPMC0_A14 13 OZ
H17 MCU_ADC0_AIN0 MCU_ADC0_AIN0 0 A 0 1.8 V VDDA_ADC_MCU ADC12BT
K18 MCU_ADC0_AIN1 MCU_ADC0_AIN1 0 A 0 1.8 V VDDA_ADC_MCU ADC12BT
M17 MCU_ADC0_AIN2 MCU_ADC0_AIN2 0 A 0 1.8 V VDDA_ADC_MCU ADC12BT
L18 MCU_ADC0_AIN3 MCU_ADC0_AIN3 0 A 0 1.8 V VDDA_ADC_MCU ADC12BT
J18 MCU_ADC0_AIN4 MCU_ADC0_AIN4 0 A 0 1.8 V VDDA_ADC_MCU ADC12BT
J17 MCU_ADC0_AIN5 MCU_ADC0_AIN5 0 A 0 1.8 V VDDA_ADC_MCU ADC12BT
K17 MCU_ADC0_AIN6 MCU_ADC0_AIN6 0 A 0 1.8 V VDDA_ADC_MCU ADC12BT
L17 MCU_ADC0_AIN7 MCU_ADC0_AIN7 0 A 0 1.8 V VDDA_ADC_MCU ADC12BT
G21 MCU_I2C0_SCL MCU_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 Yes
WKUP_GPIO0_66 7 IO pad
G20 MCU_I2C0_SDA MCU_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 Yes
WKUP_GPIO0_67 7 IO pad
A17 MCU_MCAN0_RX MCU_MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/0 Yes
WKUP_GPIO0_63 7 IO pad
A16 MCU_MCAN0_TX MCU_MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/0 Yes
WKUP_GPIO0_62 7 IO pad
D9 MCU_MDIO0_MDC MCU_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 1/0
WKUP_GPIO0_55 7 IO pad
C9 MCU_MDIO0_MDIO MCU_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 1/0
WKUP_GPIO0_54 7 IO pad
B6 MCU_OSPI0_CLK MCU_OSPI0_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD
MCU_HYPERBUS0_CK 1 O
WKUP_GPIO0_16 7 IO pad
B7 MCU_OSPI0_DQS MCU_OSPI0_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0
MCU_HYPERBUS0_RWDS 1 IO 0
WKUP_GPIO0_18 7 IO pad
C8 MCU_OSPI0_LBCLKO MCU_OSPI0_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0
MCU_HYPERBUS0_CKn 1 O
WKUP_GPIO0_17 7 IO pad
D6 MCU_OSPI0_CSn0 MCU_OSPI0_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 1/0
MCU_HYPERBUS0_CSn0 1 O
WKUP_GPIO0_27 7 IO pad
D7 MCU_OSPI0_CSn1 MCU_OSPI0_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 1/0
MCU_HYPERBUS0_RESETn 1 O
WKUP_GPIO0_28 7 IO pad
C6 MCU_OSPI0_CSn2 MCU_OSPI0_CSn2 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD
MCU_OSPI0_CSn2 1 O
MCU_HYPERBUS0_RESETOn 2 I I
MCU_HYPERBUS0_WPn 3 O
MCU_HYPERBUS0_CSn1 4 O
MCU_OSPI0_RESET_OUT0 6 O
WKUP_GPIO0_30 7 IO pad
D5 MCU_OSPI0_CSn3 MCU_OSPI0_CSn3 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD
MCU_OSPI0_CSn3 1 O
MCU_HYPERBUS0_INTn 2 I I
MCU_HYPERBUS0_WPn 3 O
MCU_OSPI0_RESET_OUT1 5 O
MCU_OSPI0_ECC_FAIL 6 I 1
WKUP_GPIO0_31 7 IO pad
D8 MCU_OSPI0_D0 MCU_OSPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/0
MCU_HYPERBUS0_DQ0 1 IO 0
WKUP_GPIO0_19 7 IO pad
BOOTMODE00 Bootstrap I
C7 MCU_OSPI0_D1 MCU_OSPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/0
MCU_HYPERBUS0_DQ1 1 IO 0
WKUP_GPIO0_20 7 IO pad
BOOTMODE01 Bootstrap I
C5 MCU_OSPI0_D2 MCU_OSPI0_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/0
MCU_HYPERBUS0_DQ2 1 IO 0
WKUP_GPIO0_21 7 IO pad
A5 MCU_OSPI0_D3 MCU_OSPI0_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/0
MCU_HYPERBUS0_DQ3 1 IO 0
WKUP_GPIO0_22 7 IO pad
A6 MCU_OSPI0_D4 MCU_OSPI0_D4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/0
MCU_HYPERBUS0_DQ4 1 IO 0
WKUP_GPIO0_23 7 IO pad
BOOTMODE02 Bootstrap I
B8 MCU_OSPI0_D5 MCU_OSPI0_D5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/0
MCU_HYPERBUS0_DQ5 1 IO 0
WKUP_GPIO0_24 7 IO pad
BOOTMODE03 Bootstrap I
A8 MCU_OSPI0_D6 MCU_OSPI0_D6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/0
MCU_HYPERBUS0_DQ6 1 IO 0
WKUP_GPIO0_25 7 IO pad
A7 MCU_OSPI0_D7 MCU_OSPI0_D7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MCU Yes LVCMOS PU/PD 0 1/0
MCU_HYPERBUS0_DQ7 1 IO 0
WKUP_GPIO0_26 7 IO pad
G19 MCU_PORz MCU_PORz I 1.8 V VDDA_WKUP, VDDA_POR_WKUP Yes FS RESET
B13 MCU_RESETSTATz MCU_RESETSTATz 0 O PD 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD
WKUP_GPIO0_79 7 IO pad
A18 MCU_RESETz MCU_RESETz 0 I 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD
B10 MCU_RGMII1_RXC MCU_RGMII1_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 1/0
MCU_RMII1_REF_CLK 1 I 0
WKUP_GPIO0_49 7 IO pad
A11 MCU_RGMII1_RX_CTL MCU_RGMII1_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 1/0
MCU_RMII1_RX_ER 1 I 0
WKUP_GPIO0_43 7 IO pad
A12 MCU_RGMII1_TXC MCU_RGMII1_TXC 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 1/0
MCU_RMII1_TX_EN 1 O
WKUP_GPIO0_48 7 IO pad
D11 MCU_RGMII1_TX_CTL MCU_RGMII1_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 1/0
MCU_RMII1_CRS_DV 1 I 0
WKUP_GPIO0_29 7 IO pad
A9 MCU_RGMII1_RD0 MCU_RGMII1_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 1/0
MCU_RMII1_RXD0 1 I 0
WKUP_GPIO0_53 7 IO pad
B9 MCU_RGMII1_RD1 MCU_RGMII1_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 1/0
MCU_RMII1_RXD1 1 I 0
WKUP_GPIO0_52 7 IO pad
A10 MCU_RGMII1_RD2 MCU_RGMII1_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 1/0
MCU_TIMER_IO5 1 IO 0
WKUP_GPIO0_51 7 IO pad
C10 MCU_RGMII1_RD3 MCU_RGMII1_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 0 1/0
MCU_TIMER_IO4 1 IO 0
WKUP_GPIO0_50 7 IO pad
D10 MCU_RGMII1_TD0 MCU_RGMII1_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 1/0
MCU_RMII1_TXD0 1 O
WKUP_GPIO0_47 7 IO pad
B11 MCU_RGMII1_TD1 MCU_RGMII1_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 1/0
MCU_RMII1_TXD1 1 O
WKUP_GPIO0_46 7 IO pad
B12 MCU_RGMII1_TD2 MCU_RGMII1_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 1/0
MCU_TIMER_IO3 1 IO 0
MCU_ADC_EXT_TRIGGER1 3 I 0
WKUP_GPIO0_45 7 IO pad
C12 MCU_RGMII1_TD3 MCU_RGMII1_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MCU Yes LVCMOS PU/PD 1/0
MCU_TIMER_IO2 1 IO 0
MCU_ADC_EXT_TRIGGER0 3 I 0
WKUP_GPIO0_44 7 IO pad
G18 MCU_SAFETY_ERRORn MCU_SAFETY_ERRORn 0 IO OFF 0 1.8 V VDDA_WKUP, VDDA_POR_WKUP Yes LVCMOS PU/PD
C13 MCU_SPI0_CLK MCU_SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/0 Yes
WKUP_GPIO0_56 7 IO pad
MCU_BOOTMODE00 Bootstrap I
A19 MCU_SPI0_CS0 MCU_SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 1/0 Yes
MCU_TIMER_IO1 4 IO 0
WKUP_GPIO0_59 7 IO pad
A20 MCU_SPI0_D0 MCU_SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/0 Yes
WKUP_GPIO0_57 7 IO pad
MCU_BOOTMODE01 Bootstrap I
B17 MCU_SPI0_D1 MCU_SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/0 Yes
MCU_TIMER_IO0 4 IO 0
WKUP_GPIO0_58 7 IO pad
MCU_BOOTMODE02 Bootstrap I
P20 MMC0_CALPAD MMC0_CALPAD A 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD
P18 MMC0_CLK MMC0_CLK O 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD
R17 MMC0_CMD MMC0_CMD IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
P19 MMC0_DS MMC0_DS IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
P21 MMC1_CLK MMC1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 0
UART8_RXD 1 I 1
TIMER_IO4 3 IO 0
UART4_CTSn 5 I 1
GPIO0_66 7 IO pad
SPI1_CLK 8 IO 0
UART0_RTSn 9 O
I2C6_SDA 10 IOD 1
M20 MMC1_CMD MMC1_CMD 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1
UART8_TXD 1 O
TIMER_IO5 3 IO 0
UART4_RTSn 5 O
GPIO0_67 7 IO pad
SPI1_D1 8 IO 0
I2C6_SCL 10 IOD 1
R16 MMC0_DAT0 MMC0_DAT0 IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
P17 MMC0_DAT1 MMC0_DAT1 IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
R18 MMC0_DAT2 MMC0_DAT2 IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
R20 MMC0_DAT3 MMC0_DAT3 IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
R19 MMC0_DAT4 MMC0_DAT4 IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
P16 MMC0_DAT5 MMC0_DAT5 IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
R21 MMC0_DAT6 MMC0_DAT6 IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
T21 MMC0_DAT7 MMC0_DAT7 IO 1.8 V VDDS_MMC0, VDDA_0P8_DLL_MMC0 eMMCPHY PU/PD 1
M19 MMC1_DAT0 MMC1_DAT0 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1
UART7_RTSn 1 O
ECAP1_IN_APWM_OUT 2 IO IO
TIMER_IO3 3 IO 0
UART4_TXD 5 O
GPIO0_65 7 IO pad
SPI1_D0 8 IO 0
UART5_RTSn 9 O
I2C4_SCL 10 IOD 1
UART2_TXD 11 O
N21 MMC1_DAT1 MMC1_DAT1 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1
UART7_CTSn 1 I 1
ECAP0_IN_APWM_OUT 2 IO IO
TIMER_IO2 3 IO 0
UART4_RXD 5 I 1
GPIO0_64 7 IO pad
SPI1_CS2 8 IO 1
UART5_CTSn 9 I 1
I2C4_SDA 10 IOD 1
UART2_RXD 11 I 1
N20 MMC1_DAT2 MMC1_DAT2 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1
UART7_TXD 1 O
TIMER_IO1 3 IO 0
GPIO0_63 7 IO pad
SPI1_CS1 8 IO 1
CPTS0_TS_SYNC 9 O
I2C3_SDA 10 IOD 1
UART5_TXD 11 O
N19 MMC1_DAT3 MMC1_DAT3 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1
UART7_RXD 1 I 1
PCIE1_CLKREQn 2 IO IO
TIMER_IO0 3 IO 0
GPIO0_62 7 IO pad
SPI1_CS0 8 IO 1
UART0_CTSn 9 I 1
I2C3_SCL 10 IOD 1
UART5_RXD 11 I 1
K19 OSC1_XI OSC1_XI I 1.8 V VDDA_OSC1 Yes HFOSC
J19 OSC1_XO OSC1_XO O 1.8 V VDDA_OSC1 Yes HFOSC
C15 PMIC_POWER_EN1 PMIC_POWER_EN1 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD Yes
MCU_I3C0_SDAPULLEN 5 OD
WKUP_GPIO0_68 7 IO pad
T19 PMIC_WAKE0n PMIC_WAKE0n 0 OD OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
RGMII4_TD1 4 O
GPIO0_1 7 IO pad
H20 PORz PORz 0 I 0 1.8 V VDDA_WKUP, VDDA_POR_WKUP Yes FS RESET
U2 RESETSTATz RESETSTATz 0 O PD 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
A15 RESET_REQz RESET_REQz 0 I OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD
AA20 RMII1_CRS_DV RMII1_CRS_DV 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/0 Yes
RGMII1_RD2 4 I 0
RMII1_CRS_DV 5 I 0
GPIO0_4 7 IO pad
EHRPWM2_B 9 IO 0
TRC_DATA7 10 O
UART4_TXD 11 O
MCASP1_AXR1 12 IO 0
GPMC0_AD2 14 IO 0
Y17 RMII1_RX_ER RMII1_RX_ER 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/0 Yes
RGMII1_RD3 4 I 0
RMII1_RX_ER 5 I 0
GPIO0_5 7 IO pad
EHRPWM2_A 9 IO 0
TRC_DATA6 10 O
UART6_TXD 11 O
MCASP1_AXR0 12 IO 0
GPMC0_AD3 14 IO 0
V17 RMII1_TX_EN RMII1_TX_EN 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII4_RXC 4 I 0
RMII1_TX_EN 5 O
GPIO0_7 7 IO pad
EQEP2_A 9 I 0
UART9_TXD 11 O
MCASP0_AXR8 12 IO 0
I2C1_SCL 13 IOD 1
GPMC0_AD5 14 IO 0
AA17 RMII1_RXD0 RMII1_RXD0 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/0 Yes
RGMII1_RD0 4 I 0
RMII1_RXD0 5 I 0
MCAN14_TX 6 O
GPIO0_2 7 IO pad
TRC_DATA9 10 O
UART5_TXD 11 O
MCASP1_AXR3 12 IO 0
GPMC0_AD0 14 IO 0
Y15 RMII1_RXD1 RMII1_RXD1 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/0 Yes
RGMII1_RD1 4 I 0
RMII1_RXD1 5 I 0
MCAN14_RX 6 I 1
GPIO0_3 7 IO pad
EHRPWM_TZn_IN2 9 I 0
TRC_DATA8 10 O
UART5_RXD 11 I 1
MCASP1_AXR2 12 IO 0
GPMC0_AD1 14 IO 0
Y16 RMII1_TXD0 RMII1_TXD0 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII1_RX_CTL 4 I 0
RMII1_TXD0 5 O
GPIO0_6 7 IO pad
EHRPWM0_SYNCO 9 O
TRC_CTL 10 O
UART6_RXD 11 I 1
MCASP0_AFSX 12 IO 0
GPMC0_AD4 14 IO 0
AA19 RMII1_TXD1 RMII1_TXD1 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1/0 Yes
RGMII1_RXC 4 I 0
RMII1_TXD1 5 O
GPIO0_8 7 IO pad
EHRPWM_TZn_IN1 9 I 0
TRC_DATA5 10 O
UART9_RXD 11 I 1
MCASP0_AXR3 12 IO 0
I2C1_SDA 13 IOD 1
GPMC0_AD6 14 IO 0
V7 SERDES0_REXT SERDES0_REXT A 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
AA8 SERDES0_REFCLK_N SERDES0_REFCLK_N IO 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
AA9 SERDES0_REFCLK_P SERDES0_REFCLK_P IO 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
AA11 SERDES0_RX0_N SERDES0_RX0_N I 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII3_RX0_N I
PCIE1_RX0_N I
USB0_SSRX1N I
AA12 SERDES0_RX0_P SERDES0_RX0_P I 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII3_RX0_P I
PCIE1_RX0_P I
USB0_SSRX1P I
W8 SERDES0_RX1_N SERDES0_RX1_N I 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII4_RX0_N I
PCIE1_RX1_N I
USB0_SSRX2N I
W9 SERDES0_RX1_P SERDES0_RX1_P I 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII4_RX0_P I
PCIE1_RX1_P I
USB0_SSRX2P I
Y7 SERDES0_RX2_N SERDES0_RX2_N I 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII1_RX0_N I
PCIE1_RX2_N I
USB0_SSRX1N I
Y8 SERDES0_RX2_P SERDES0_RX2_P I 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII1_RX0_P I
PCIE1_RX2_P I
USB0_SSRX1P I
W5 SERDES0_RX3_N SERDES0_RX3_N I 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII2_RX0_N I
PCIE1_RX3_N I
USB0_SSRX2N I
W6 SERDES0_RX3_P SERDES0_RX3_P I 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII2_RX0_P I
PCIE1_RX3_P I
USB0_SSRX2P I
W11 SERDES0_TX0_N SERDES0_TX0_N O 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII3_TX0_N O
PCIE1_TX0_N O
USB0_SSTX1N O
W12 SERDES0_TX0_P SERDES0_TX0_P O 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII3_TX0_P O
PCIE1_TX0_P O
USB0_SSTX1P O
Y10 SERDES0_TX1_N SERDES0_TX1_N O 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII4_TX0_N O
PCIE1_TX1_N O
USB0_SSTX2N O
Y11 SERDES0_TX1_P SERDES0_TX1_P O 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII4_TX0_P O
PCIE1_TX1_P O
USB0_SSTX2P O
AA5 SERDES0_TX2_N SERDES0_TX2_N O 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII1_TX0_N O
PCIE1_TX2_N O
USB0_SSTX1N O
AA6 SERDES0_TX2_P SERDES0_TX2_P O 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII1_TX0_P O
PCIE1_TX2_P O
USB0_SSTX1P O
Y4 SERDES0_TX3_N SERDES0_TX3_N O 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII2_TX0_N O
PCIE1_TX3_N O
USB0_SSTX2N O
Y5 SERDES0_TX3_P SERDES0_TX3_P O 0.8 V VDDA_0P8_SERDES0, VDDA_1P8_SERDES0, VDDA_0P8_SERDES0_C SERDES
SGMII2_TX0_P O
PCIE1_TX3_P O
USB0_SSTX2P O
V2 SOC_SAFETY_ERRORn SOC_SAFETY_ERRORn 0 IO OFF 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
Y1 SPI0_CLK SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0
UART1_CTSn 1 I 1
I2C2_SCL 2 IOD IOD
GPIO0_53 7 IO pad
W3 SPI0_CS0 SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1
UART0_CTSn 2 I I
GPIO0_51 7 IO pad
U5 SPI0_CS1 SPI0_CS1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1
CPTS0_TS_COMP 1 O
UART0_RTSn 2 O O
GPIO0_52 7 IO pad
V4 SPI0_D0 SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0
UART1_RTSn 1 O
I2C2_SDA 2 IOD IOD
GPIO0_54 7 IO pad
T5 SPI0_D1 SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0
GPIO0_55 7 IO pad
B15 TCK TCK 0 I 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD
F19 TDI TDI 0 I OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD
F21 TDO TDO 0 OZ OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD
V1 TIMER_IO0 TIMER_IO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0
ECAP1_IN_APWM_OUT 1 IO 0
SYSCLKOUT0 2 O O
UART3_CTSn 5 I 1
SPI7_D0 6 IO 0
GPIO0_60 7 IO pad
MMC1_SDCD 8 I 1
W1 TIMER_IO1 TIMER_IO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/0
ECAP2_IN_APWM_OUT 1 IO 0
OBSCLK0 2 O O
UART3_RTSn 5 O
SPI7_D1 6 IO 0
GPIO0_61 7 IO pad
MMC1_SDWP 8 I 1
PCIE1_CLKREQn 9 IO 0
U4 TMS TMS 0 I OFF 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
B20 TRSTn TRSTn 0 I 0 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD
T16 UART0_RXD UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 0/0 Yes
RGMII4_TXC 4 O
GPIO0_47 7 IO pad
GPMC0_WAIT0 14 I 0
T17 UART0_TXD UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD Yes
RGMII4_TD2 4 O
GPIO0_48 7 IO pad
GPMC0_WEn 14 O
T18 UART1_RXD UART1_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 Yes
MCAN17_TX 1 O
TIMER_IO6 3 IO 0
RGMII4_TD3 4 O
GPIO0_49 7 IO pad
GPMC0_OEn_REn 14 O
T20 UART1_TXD UART1_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD Yes
MCAN17_RX 1 I 1
TIMER_IO7 3 IO 0
RGMII4_TX_CTL 4 O
GPIO0_50 7 IO pad
GPMC0_CSn0 14 O
V14 UART2_RXD UART2_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 0/0 Yes
RGMII2_TD2 4 O
RMII2_CRS_DV 5 I 0
GPIO0_39 7 IO pad
SPI6_CLK 8 IO 0
GPMC0_CLKOUT 9 O
GPMC0_FCLK_MUX 10 O
UART2_RXD 11 I 1
MCASP2_AXR3 12 IO 0
OBSCLK2 14 O
V13 UART2_TXD UART2_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD Yes
RGMII2_TD3 4 O
RMII2_RX_ER 5 I 0
GPIO0_40 7 IO pad
SPI6_D0 8 IO 0
UART2_TXD 11 O
MCASP2_AFSX 12 IO 0
W14 UART8_RXD UART8_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 1 Yes
I2C4_SCL 2 IOD IOD
MDIO0_MDIO 5 IO 0
GPIO0_42 7 IO pad
TRC_DATA22 10 O
UART8_RXD 11 I 1
MCASP2_AFSR 12 IO 0
MCASP2_AXR4 13 IO 0
W19 UART8_TXD UART8_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD Yes
SPI1_CS3 1 IO 1
I2C4_SDA 2 IOD IOD
MDIO0_MDC 5 O
GPIO0_43 7 IO pad
TRC_DATA23 10 O
UART8_TXD 11 O
MCASP2_ACLKR 12 IO 0
MCASP2_AXR5 13 IO 0
AA3 USB0_DM USB0_DM IO 3.3 V VDDA_0P8_USB ,VDDA_1P8_USB, VDDA_3P3_USB USB2PHY
AA2 USB0_DP USB0_DP IO 3.3 V VDDA_0P8_USB ,VDDA_1P8_USB, VDDA_3P3_USB USB2PHY
T4 USB0_DRVVBUS USB0_DRVVBUS 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
GPIO0_68 7 IO pad
V6 USB0_ID USB0_ID A 3.3 V VDDA_0P8_USB ,VDDA_1P8_USB, VDDA_3P3_USB USB2PHY
V5 USB0_RCALIB USB0_RCALIB IO 3.3 V VDDA_0P8_USB ,VDDA_1P8_USB, VDDA_3P3_USB USB2PHY
Y2 USB0_VBUS USB0_VBUS A 5.0 V VDDA_0P8_USB ,VDDA_1P8_USB, VDDA_3P3_USB USB2PHY
K14, P14 VDDAR_CORE VDDAR_CORE PWR
J11, M10 VDDAR_CPU VDDAR_CPU PWR
H12, J14 VDDAR_MCU VDDAR_MCU PWR
K7 VDDA_0P8_PLL_DDR VDDA_0P8_PLL_DDR PWR
P7 VDDA_0P8_USB VDDA_0P8_USB PWR
M18 VDDA_0P8_DLL_MMC0 VDDA_0P8_DLL_MMC0 PWR
R8, T7, U8 VDDA_0P8_SERDES0 VDDA_0P8_SERDES0 PWR
R9 VDDA_0P8_SERDES0_C VDDA_0P8_SERDES0_C PWR
R6 VDDA_1P8_USB VDDA_1P8_USB PWR
P8 VDDA_1P8_SERDES0 VDDA_1P8_SERDES0 PWR
R7 VDDA_3P3_USB VDDA_3P3_USB PWR
J16 VDDA_ADC_MCU VDDA_ADC_MCU PWR
F15 VDDA_MCU_PLLGRP0 VDDA_MCU_PLLGRP0 PWR
F16 VDDA_MCU_TEMP VDDA_MCU_TEMP PWR
G17 VDDA_OSC1 VDDA_OSC1 PWR
N14 VDDA_PLLGRP0 VDDA_PLLGRP0 PWR
N9 VDDA_PLLGRP4 VDDA_PLLGRP4 PWR
J9 VDDA_PLLGRP6 VDDA_PLLGRP6 PWR
L7 VDDA_PLLGRP8 VDDA_PLLGRP8 PWR
J15 VDDA_POR_WKUP VDDA_POR_WKUP PWR
J8 VDDA_TEMP0 VDDA_TEMP0 PWR
P15 VDDA_TEMP1 VDDA_TEMP1 PWR
H16 VDDA_WKUP VDDA_WKUP PWR
N6, P6 VDDSHV0 VDDSHV0 PWR
E13, E14, F13, F14 VDDSHV0_MCU VDDSHV0_MCU PWR
E7, E8, F8 VDDSHV1_MCU VDDSHV1_MCU PWR
T10, U11, U9 VDDSHV2 VDDSHV2 PWR
F11, F12, G11 VDDSHV2_MCU VDDSHV2_MCU PWR
K16, L16 VDDSHV5 VDDSHV5 PWR
A1, G7, H6, J7, K6, M5, U1 VDDS_DDR VDDS_DDR PWR
F7, L6 VDDS_DDR_BIAS VDDS_DDR_BIAS PWR
J6 VDDS_DDR_C VDDS_DDR_C PWR
M16, N16 VDDS_MMC0 VDDS_MMC0 PWR
H8, K12, L13, M12, M14, N13, N15, N7, P10, P12, R11, R13, R15 VDD_CORE VDD_CORE PWR
J10, L11, M9, N11, N8 VDD_CPU VDD_CPU PWR
G9, H10, H14, J13, K15 VDD_MCU VDD_MCU PWR
G13 VDD_MCU_WAKE1 VDD_MCU_WAKE1 PWR
P11 VDD_WAKE0 VDD_WAKE0 PWR
G15 VMON1_ER_VSYS VMON1_ER_VSYS PWR
D16 VMON2_IR_VCPU VMON2_IR_VCPU PWR
E17 VMON3_IR_VEXT1P8 VMON3_IR_VEXT1P8 PWR
F17 VMON4_IR_VEXT1P8 VMON4_IR_VEXT1P8 PWR
L14 VMON5_IR_VEXT3P3 VMON5_IR_VEXT3P3 PWR
N17 VPP_CORE VPP_CORE PWR
E11 VPP_MCU VPP_MCU PWR
B5,AA1, AA10, AA13, AA4, AA7, C11, D15, D17, D3, E10, E12, E15, E16, E6, E9, F1, G10, G12, G16, G6, G8, H11, H13, H15, H19, H4, H7, H9, J1, J12, J21, K11, K13, K3, L12, L19, L5, M11, M13, M15, M21, M6, M8, N10, N12, N3, P13, P5, P9, R10, R12, R14, T11, T2, T6, T8, T9, U10, U7, V11, V12, V9, W10, W13, W18, W4, W7, Y12, Y3, Y6, Y9 VSS VSS GND
B18 WKUP_GPIO0_0 MCU_SPI1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 Yes
MCU_SPI1_CLK 1 IO 0
WKUP_GPIO0_0 7 IO pad
MCU_BOOTMODE03 Bootstrap I
B19 WKUP_GPIO0_1 MCU_SPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/0 Yes
MCU_SPI1_D0 1 IO 0
WKUP_GPIO0_1 7 IO pad
MCU_BOOTMODE04 Bootstrap I
D14 WKUP_GPIO0_2 MCU_SPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 1/0 Yes
MCU_SPI1_D1 1 IO 0
WKUP_GPIO0_2 7 IO pad
MCU_BOOTMODE05 Bootstrap I
B21 WKUP_GPIO0_3 MCU_SPI1_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 Yes
MCU_SPI1_CS0 1 IO 1
WKUP_GPIO0_3 7 IO pad
D13 WKUP_GPIO0_4 MCU_MCAN1_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD Yes
MCU_MCAN1_TX 1 O
MCU_SPI0_CS3 2 IO IO
MCU_ADC_EXT_TRIGGER0 3 I pad
WKUP_GPIO0_4 7 IO pad
B16 WKUP_GPIO0_5 MCU_MCAN1_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 Yes
MCU_MCAN1_RX 1 I 1
MCU_SPI1_CS3 2 IO IO
MCU_ADC_EXT_TRIGGER1 3 I pad
WKUP_GPIO0_5 7 IO pad
C14 WKUP_GPIO0_6 WKUP_UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 Yes
WKUP_UART0_CTSn 1 I 1
MCU_CPTS0_HW1TSPUSH 2 I I
MCU_I2C1_SCL 3 IOD 1
WKUP_GPIO0_6 7 IO pad
C18 WKUP_GPIO0_7 WKUP_UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD Yes
WKUP_UART0_RTSn 1 O
MCU_CPTS0_HW2TSPUSH 2 I I
MCU_I2C1_SDA 3 IOD 1
WKUP_GPIO0_7 7 IO pad
C21 WKUP_GPIO0_8 MCU_I2C1_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 Yes
MCU_I2C1_SCL 1 IOD 1
MCU_CPTS0_TS_SYNC 2 O O
MCU_I3C0_SCL 3 IO 1
MCU_TIMER_IO6 4 IO 0
WKUP_GPIO0_8 7 IO pad
C19 WKUP_GPIO0_9 MCU_I2C1_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 Yes
MCU_I2C1_SDA 1 IOD 1
MCU_CPTS0_TS_COMP 2 O O
MCU_I3C0_SDA 3 IO 1
MCU_TIMER_IO7 4 IO 0
WKUP_GPIO0_9 7 IO pad
C20 WKUP_GPIO0_10 MCU_EXT_REFCLK0 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 Yes
MCU_EXT_REFCLK0 1 I 0
MCU_UART0_TXD 2 O O
MCU_ADC_EXT_TRIGGER0 3 I 0
MCU_CPTS0_RFT_CLK 4 I 0
MCU_SYSCLKOUT0 5 O
WKUP_GPIO0_10 7 IO pad
C16 WKUP_GPIO0_11 MCU_OBSCLK0 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD Yes
MCU_OBSCLK0 1 O
MCU_UART0_RXD 2 I I
MCU_ADC_EXT_TRIGGER1 3 I 0
MCU_TIMER_IO1 4 IO 0
MCU_I3C0_SDAPULLEN 5 OD
MCU_CLKOUT0 6 OZ
WKUP_GPIO0_11 7 IO pad
D19 WKUP_GPIO0_12 MCU_UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD Yes
MCU_SPI0_CS1 1 IO
WKUP_GPIO0_12 7 IO pad
MCU_BOOTMODE08 Bootstrap I
D20 WKUP_GPIO0_13 MCU_UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 Yes
MCU_SPI1_CS1 1 IO
WKUP_GPIO0_13 7 IO pad
MCU_BOOTMODE09 Bootstrap I
E20 WKUP_GPIO0_14 MCU_UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 Yes
MCU_SPI0_CS2 1 IO
MCU_TIMER_IO8 4 IO 0
WKUP_GPIO0_14 7 IO pad
MCU_BOOTMODE06 Bootstrap I
E21 WKUP_GPIO0_15 MCU_UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD Yes
MCU_SPI1_CS2 1 IO
MCU_TIMER_IO9 4 IO 0
WKUP_GPIO0_15 7 IO pad
MCU_BOOTMODE07 Bootstrap I
D21 WKUP_GPIO0_77 MCU_TIMER_IO6 4 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 Yes
WKUP_GPIO0_77 7 IO pad
BOOTMODE04 Bootstrap I
E19 WKUP_GPIO0_78 MCU_TIMER_IO7 4 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 0 Yes
WKUP_GPIO0_78 7 IO pad
BOOTMODE05 Bootstrap I
D18 WKUP_GPIO0_80 WKUP_GPIO0_80 7 IO OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD pad Yes
BOOTMODE06 Bootstrap I
C17 WKUP_GPIO0_81 WKUP_LF_CLKIN 1 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD pad Yes
WKUP_GPIO0_81 7 IO pad
BOOTMODE07 Bootstrap I
E18 WKUP_GPIO0_84 PMIC_WAKE1n 0 OD OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD
MCU_EXT_REFCLK0 1 I 0
MCU_CPTS0_RFT_CLK 2 I I
WKUP_GPIO0_84 7 IO pad
F20 WKUP_I2C0_SCL WKUP_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 Yes
WKUP_GPIO0_64 7 IO pad
H21 WKUP_I2C0_SDA WKUP_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MCU Yes I2C OD FS 1 Yes
WKUP_GPIO0_65 7 IO pad
K21 WKUP_OSC0_XI WKUP_OSC0_XI I 1.8 V VDDA_WKUP, VDDA_POR_WKUP Yes HFOSC
L21 WKUP_OSC0_XO WKUP_OSC0_XO O 1.8 V VDDA_WKUP, VDDA_POR_WKUP Yes HFOSC
B14 WKUP_UART0_RXD WKUP_UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1 1/0 Yes
WKUP_GPIO0_60 7 IO pad
A14 WKUP_UART0_TXD WKUP_UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MCU Yes LVCMOS PU/PD 1/0 Yes
WKUP_GPIO0_61 7 IO pad

The following list describes the table column headers:

  1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
    Note:

    Table 6-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 6.3, Signal Descriptions.

  4. MUXMODE: Multiplexing mode number:
    1. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode.
      Note:

      The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column.

    2. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
    3. An empty box means Not Applicable.
  5. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • OD = Open drain terminal - Output
    • IO = Input or Output
    • IOD = Open drain terminal - Input or Output
    • IOZ = Input, Output or Three-state terminal
    • OZ = Output or Three-state terminal
    • A = Analog
    • PWR = Power
    • GND = Ground
    • CAP = LDO Capacitor.
  6. BALL RESET STATE: The state of the terminal at power-on reset:
    • DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable.
  7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the RESETSTATz and MCU_RESETSTATz signals.
    An empty box means Not Applicable.
  8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
    An empty box means Not Applicable.
  9. POWER: The voltage supply that powers the terminal IO buffers.
    An empty box means Not Applicable.
  10. HYS: Indicates if the input buffer has hysteresis:
    • Yes: With hysteresis
    • No: Without hysteresis

      An empty box means No.

    For more information, see the hysteresis values in Section 7.6, Electrical Characteristics.

  11. BUFFER TYPE: This column describes the associated output buffer type

    An empty box means Not Applicable.

    For drive strength of the associated output buffer, refer to Section 7.6, Electrical Characteristics.

  12. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • PU: Internal pullup
    • PD: Internal pulldown
    • PU/PD: Internal pullup and pulldown
    • An empty box means No pull.
  13. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "pad" level) when the peripheral pin function is not selected by any of the PINCNTLx registers.
    • 0: Logic 0 driven on the input signal port of the peripheral.
    • 1: Logic 1 driven on the input signal port of the peripheral.
    • pad: Logic state of the pad is driven on the input signal port of the peripheral.
    • An empty box means Not Applicable.
  14. RXACTIVE / TXDISABLE: This column indicates the default value of the RXACTIVE / TXDISABLE bits in the PADCONFIG register.
    • RXACTIVE: 0 = receiver disabled, 1 = receiver enabled.
    • TXDISABLE: 0 = driver enabled, 1 = driver disabled.
    • An empty box means Not Applicable.
    Note:

    Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (HiZ mode is not an input signal).

    Note:

    When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

  15. IO RET: Indicates if wakeup and IO retention are supported.