SPRSP57E Data sheet

SPRSP57E april 2020 – june 2023 DRA821U , DRA821U-Q1

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ALM|433

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

SUPPLY NAME	DESCRIPTION		MIN⁽¹⁾	NOM	MAX⁽¹⁾	UNIT
VDD_CORE⁽³⁾	Boot/Active voltage for MAIN domain core supply		0.76⁽¹⁾	0.8	0.84⁽¹⁾	V
VDD_MCU	Boot/Active voltage for MCUSS core supply		0.76⁽¹⁾	0.8	0.89⁽¹⁾	V
VDD_CPU	Boot voltage for CPU core supply, applied at cold power up event		0.76⁽¹⁾	0.8	0.84⁽¹⁾	V
VDD_CPU	Active voltage for CPU core supply, after AVS mode enabled in software		AVS⁽⁵⁾-5%⁽¹⁾	AVS⁽⁵⁾	AVS⁽⁵⁾+5%⁽¹⁾	V
VDD_CPU AVS Range	Efuse valid voltage range for VDD_CPU voltage		0.6		0.9	V
VDD_MCU_WAKE1	Core supply for MCU WAKE function		0.76	0.8	0.89	V
VDD_WAKE0	Core supply for MAIN domain WAKE function which includes all "CANUART" IO.		0.76	0.8	0.89	V
VDDA_0P8_DLL_MMC0	MMC PLL analog supply		0.76	0.8	0.84	V
VDDAR_CORE	Main domain RAM supply		0.81	0.85	0.89	V
VDDAR_MCU	MCUSS RAM supply		0.81	0.85	0.89	V
VDDAR_CPU	CPU RAM supply		0.81	0.85	0.89	V
VDDA_0P8_SERDES0⁽³⁾	SERDES0 analog supply low		0.76	0.8	0.84	V
VDDA_0P8_SERDES0_C⁽³⁾	SERDES0-1 clock supply		0.76	0.8	0.84	V
VDDA_0P8_USB⁽³⁾	USB 0.8v analog supply		0.76	0.8	0.84	V
VDDA_1P8_USB	USB 1.8v analog supply		1.71	1.8	1.89	V
VDDA_1P8_SERDES0	SERDES0 analog supply high		1.71	1.8	1.89	V
VDDA_3P3_USB	USB 3.3v analog supply		3.14	3.3	3.46	V
VDDA_MCU_PLLGRP0	Analog supply for MCU PLL Group 0		1.71	1.8	1.89	V
VDDA_PLLGRP0	Analog supply for MAIN PLL Group 0		1.71	1.8	1.89	V
VDDA_PLLGRP4	Analog supply for MAIN PLL Group 4		1.71	1.8	1.89	V
VDDA_PLLGRP6	Analog supply for MAIN PLL Group 6		1.71	1.8	1.89	V
VDDA_PLLGRP8	Analog supply for MAIN PLL Group 8		1.71	1.8	1.89	V
VDDA_WKUP	Oscillator supply for WKUP domain		1.71	1.8	1.89	V
VDDA_ADC_MCU	ADC analog supply		1.71	1.8	1.89	V
VDDA_0P8_PLL_DDR	DDR PLL analog supply		0.76	0.8	0.84	V
VDDA_MCU_TEMP	Analog supply for temperature sensor 0 in MCU domain		1.71	1.8	1.89	V
VDDA_POR_WKUP	WKUP domain analog supply		1.71	1.8	1.89	V
VDDA_TEMP0	Analog supply for temperature sensor 0		1.71	1.8	1.89	V
VDDA_TEMP1	Analog supply for temperature sensor 1		1.71	1.8	1.89	V
VDDS_DDR⁽²⁾	DDR inteface power supply		1.05	1.1	1.15	V
VDDS_DDR_BIAS⁽²⁾	Bias supply for LPDDR4		1.05	1.1	1.15	V
VDDS_DDR_C⁽²⁾	IO power for DDR Memory Clock Bit (MCB) macro		1.05	1.1	1.15	V
VDDS_MMC0	MMC0 IO supply		1.71	1.8	1.89	V
VDDA_OSC1	HFOSC1 supply		1.71	1.8	1.89	V
VDDA_*	Peak to Peak Noise for all VDDA inputs				25	mV
VDDSHV0	IO supply for main domain general	1.8-V operation	1.71	1.8	1.89	V
VDDSHV0	IO supply for main domain general	3.3-V operation	3.14	3.3	3.46	V
VDDSHV0_MCU	IO supply MCUSS general IO group, and MCU and Main domain warm reset pins	1.8-V operation	1.71	1.8	1.89	V
VDDSHV0_MCU		3.3-V operation	3.14	3.3	3.46	V
VDDSHV1_MCU	IO supply for MCUSS IO group 1	1.8-V operation	1.71	1.8	1.89	V
VDDSHV1_MCU	IO supply for MCUSS IO group 1	3.3-V operation	3.14	3.3	3.46	V
VDDSHV2	IO supply for main domain IO group 2	1.8-V operation	1.71	1.8	1.89	V
VDDSHV2	IO supply for main domain IO group 2	3.3-V operation	3.14	3.3	3.46	V
VDDSHV2_MCU	IO supply for MCUSS IO group 2	1.8-V operation	1.71	1.8	1.89	V
VDDSHV2_MCU	IO supply for MCUSS IO group 2	3.3-V operation	3.14	3.3	3.46	V
VDDSHV5	IO supply for main domain IO group 5	1.8-V operation	1.71	1.8	1.89	V
VDDSHV5	IO supply for main domain IO group 5	3.3-V operation	3.14	3.3	3.46	V
USB0_VBUS	Voltage range for USB VBUS comparator input		0	See⁽⁶⁾	3.46	V
USB0_ID	Voltage range for the USB ID input			See⁽⁴⁾		V
VSS	Ground			0		V
T_J	Operating junction temperature range	Automotive	–40		125	°C
		Extended	–40		105	°C
		Commercial	0		90	°C

(1) For all VDD* supply inputs, the voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth. This is required for all supply inputs, but special care should be given to the VDD_CORE, VDD_MCU, and VDD_CPU domains which have higher transient current demand compared to other rails.

(2) A single 1.1-V source must drive all three VDDS_DDR, VDDS_DDR_BIAS, VDDS_DDR_C supplies. These supplies are required to still be powered with LPDDR4 voltage ranges, even If DDR interface is unused.

(3) A single 0.8-V source must drive the VDD_CORE and VDDA_0P8_ PHY input supplies. Also, include Analog filter components on the individual VDDA_0P8_ PHY input supplies for interfaces that are used in the system.

(4) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source.

(5) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry.

(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.3, USB VBUS Design Guidelines