SPRSP35J February   2019  – August 2021 DRA829J , DRA829V

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW9G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EHRPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MCU Domain
        2. 6.3.21.2 MAIN Domain
      22. 6.3.22 UFS
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 PRU_ICSSG [Currently Not Supported]
        1. 6.3.23.1 MAIN Domain
      24. 6.3.24 MCASP
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 DSS
        1. 6.3.25.1 MAIN Domain
      26. 6.3.26 DP
        1. 6.3.26.1 MAIN Domain
      27. 6.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
        1. 6.3.27.1 MAIN Domain
      28. 6.3.28 DSI_TX
        1. 6.3.28.1 MAIN Domain
      29. 6.3.29 VPFE
        1. 6.3.29.1 MAIN Domain
      30. 6.3.30 DMTIMER
        1. 6.3.30.1 MAIN Domain
        2. 6.3.30.2 MCU Domain
      31. 6.3.31 Emulation and Debug
        1. 6.3.31.1 MAIN Domain
      32. 6.3.32 System and Miscellaneous
        1. 6.3.32.1 Boot Mode Configuration
          1. 6.3.32.1.1 MAIN Domain
          2. 6.3.32.1.2 MCU Domain
        2. 6.3.32.2 Clock
          1. 6.3.32.2.1 MAIN Domain
          2. 6.3.32.2.2 WKUP Domain
        3. 6.3.32.3 System
          1. 6.3.32.3.1 MAIN Domain
          2. 6.3.32.3.2 WKUP Domain
        4. 6.3.32.4 EFUSE
      33. 6.3.33 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On-Hour (POH) Limits
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.7.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 7.7.3  HFOSC/LFOSC Electrical Characteristics
      4. 7.7.4  eMMCPHY Electrical Characteristics
      5. 7.7.5  SDIO Electrical Characteristics
      6. 7.7.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 7.7.7  ADC12B Electrical Characteristics
      8. 7.7.8  MLB LVCMOS Electrical Characteristics
      9. 7.7.9  LVCMOS Electrical Characteristics
      10. 7.7.10 USB2PHY Electrical Characteristics
      11. 7.7.11 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      12. 7.7.12 UFS M-PHY Electrical Characteristics
      13. 7.7.13 eDP/DP AUX-PHY Electrical Characteristics
      14. 7.7.14 DDR0 Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics for ALF Package
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
        6. 7.10.2.6 Entry and Exit of MCU Only State
        7. 7.10.2.7 Entry and Exit of DDR Retention State
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
          6. 7.10.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.6.1 WKUP_LFOSC0 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Module and Peripheral Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 ATL_PCLK Timing Requirements
          2. 7.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 7.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 7.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 7.10.5.2  VPFE
        3. 7.10.5.3  CPSW2G
          1. 7.10.5.3.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.3.2 CPSW2G RMII Timings
            1. 7.10.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 7.10.5.3.3 CPSW2G RGMII Timings
            1. 7.10.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        4. 7.10.5.4  CPSW9G
          1. 7.10.5.4.1 CPSW9G MDIO Interface Timings
          2. 7.10.5.4.2 CPSW9G RMII Timings
            1. 7.10.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 7.10.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 7.10.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
          3. 7.10.5.4.3 CPSW9G RGMII Timings
            1. 7.10.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 7.10.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
            3. 7.10.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 7.10.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        5. 7.10.5.5  CSI-2
        6. 7.10.5.6  DDRSS
        7. 7.10.5.7  DSS
        8. 7.10.5.8  eCAP
          1. 7.10.5.8.1 Timing Requirements for eCAP
          2. 7.10.5.8.2 Switching Characteristics for eCAP
        9. 7.10.5.9  EPWM
          1. 7.10.5.9.1 Timing Requirements for eHRPWM
          2. 7.10.5.9.2 Switching Characteristics for eHRPWM
        10. 7.10.5.10 eQEP
          1. 7.10.5.10.1 Timing Requirements for eQEP
          2. 7.10.5.10.2 Switching Characteristics for eQEP
        11. 7.10.5.11 GPIO
          1. 7.10.5.11.1 GPIO Timing Requirements
          2. 7.10.5.11.2 GPIO Switching Characteristics
        12. 7.10.5.12 GPMC
          1. 7.10.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 7.10.5.12.4 GPMC0 IOSET
        13. 7.10.5.13 HyperBus
          1. 7.10.5.13.1 Timing Requirements for HyperBus
          2. 7.10.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 7.10.5.14 I2C
        15. 7.10.5.15 I3C
        16. 7.10.5.16 MCAN
        17. 7.10.5.17 MCASP
        18. 7.10.5.18 MCSPI
          1. 7.10.5.18.1 MCSPI — Master Mode
          2. 7.10.5.18.2 MCSPI — Slave Mode
        19. 7.10.5.19 MMCSD
          1. 7.10.5.19.1 MMC0 - eMMC Interface
            1. 7.10.5.19.1.1 Legacy SDR Mode
            2. 7.10.5.19.1.2 High Speed SDR Mode
            3. 7.10.5.19.1.3 High Speed DDR Mode
            4. 7.10.5.19.1.4 HS200 Mode
          2. 7.10.5.19.2 MMC1/2 - SD/SDIO Interface
            1. 7.10.5.19.2.1 Default Speed Mode
            2. 7.10.5.19.2.2 High Speed Mode
            3. 7.10.5.19.2.3 UHS–I SDR12 Mode
            4. 7.10.5.19.2.4 UHS–I SDR25 Mode
            5. 7.10.5.19.2.5 UHS–I SDR50 Mode
            6. 7.10.5.19.2.6 UHS–I DDR50 Mode
            7. 7.10.5.19.2.7 UHS–I SDR104 Mode
        20. 7.10.5.20 CPTS
          1. 7.10.5.20.1 CPTS Timing Requirements
          2. 7.10.5.20.2 CPTS Switching Characteristics
        21. 7.10.5.21 OSPI
          1. 7.10.5.21.1 OSPI With Data Training
            1. 7.10.5.21.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.21.2 OSPI Without Data Training
            1. 7.10.5.21.2.1 OSPI Timing Requirements – SDR Mode
            2. 7.10.5.21.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.10.5.21.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.10.5.21.2.4 OSPI Switching Characteristics – DDR Mode
        22. 7.10.5.22 OLDI
          1. 7.10.5.22.1 OLDI Switching Characteristics
        23. 7.10.5.23 PCIE
        24. 7.10.5.24 Timers
          1. 7.10.5.24.1 Timing Requirements for Timers
          2. 7.10.5.24.2 Switching Characteristics for Timers
        25. 7.10.5.25 UART
          1. 7.10.5.25.1 Timing Requirements for UART
          2. 7.10.5.25.2 UART Switching Characteristics
        26. 7.10.5.26 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 JTAG Timing Requirements
            2. 7.10.6.2.1.2 JTAG Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
      3. 8.2.3 DSP C71x
      4. 8.2.4 DSP C66x
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 GPU
      2. 8.3.2 D5520MP2
      3. 8.3.3 VXE384MP2
    4. 8.4 Other Subsystems
      1. 8.4.1 MSMC
      2. 8.4.2 NAVSS
        1. 8.4.2.1 NAVSS0
        2. 8.4.2.2 MCU_NAVSS
      3. 8.4.3 PDMA Controller
      4. 8.4.4 Power Supply
      5. 8.4.5 Peripherals
        1. 8.4.5.1  ADC
        2. 8.4.5.2  ATL
        3. 8.4.5.3  CSI
          1. 8.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 8.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        4. 8.4.5.4  CPSW2G
        5. 8.4.5.5  CPSW9G
        6. 8.4.5.6  DCC
        7. 8.4.5.7  DDRSS
        8. 8.4.5.8  DSS
          1. 8.4.5.8.1 DSI
          2. 8.4.5.8.2 eDP
        9. 8.4.5.9  VPFE
        10. 8.4.5.10 eCAP
        11. 8.4.5.11 EPWM
        12. 8.4.5.12 ELM
        13. 8.4.5.13 ESM
        14. 8.4.5.14 eQEP
        15. 8.4.5.15 GPIO
        16. 8.4.5.16 GPMC
        17. 8.4.5.17 Hyperbus
        18. 8.4.5.18 I2C
        19. 8.4.5.19 I3C
        20. 8.4.5.20 MCAN
        21. 8.4.5.21 MCASP
        22. 8.4.5.22 MCRC Controller
        23. 8.4.5.23 MCSPI
        24. 8.4.5.24 MMC/SD
        25. 8.4.5.25 OSPI
        26. 8.4.5.26 PCIE
        27. 8.4.5.27 SerDes
        28. 8.4.5.28 WWDT
        29. 8.4.5.29 Timers
        30. 8.4.5.30 UART
        31. 8.4.5.31 USB
        32. 8.4.5.32 UFS
  9. 9 Applications and Implementation
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for JacintoTM 7 Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 SERDES REFCLK Design Guidelines
      4. 9.3.4 USB VBUS Design Guidelines
      5. 9.3.5 System Power Supply Monitor Design Guidelines
      6. 9.3.6 High Speed Differential Signal Routing Guidance
      7. 9.3.7 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALF|827
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.33 Power Supply

Note:

All power balls must be supplied with the voltages specified in Section 7.4, Recommended Operating Conditions, unless otherwise specified in Section 6.3, Signal Descriptions.

Table 6-124 Power Supply Signal Description
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
CAP_VDDS0(1)External capacitor connection forCAPU7
CAP_VDDS0_MCU(1)External capacitor connection forCAPK23
CAP_VDDS1(1)External capacitor connection forCAPAB21
CAP_VDDS1_MCU(1)External capacitor connection forCAPJ18
CAP_VDDS2(1)External capacitor connection forCAPY18
CAP_VDDS2_MCU(1)External capacitor connection forCAPJ19
CAP_VDDS3(1)External capacitor connection forCAPW21
CAP_VDDS4(1)External capacitor connection forCAPAA22
CAP_VDDS5(1)External capacitor connection forCAPR22
CAP_VDDS6(1)External capacitor connection forCAPV22
VDDAR_COREMAIN domain RAM supplyPWRL14, V13, V16, W19
VDDAR_CPUCPU RAM supplyPWRL11, W12
VDDAR_MCUMCUSS RAM supplyPWRK19, T19
VDDA_0P8_CSIRXCSIRX analog supply lowPWRH17
VDDA_0P8_DPDisplayport SERDES analog supply lowPWRG12, J12
VDDA_0P8_DP_CDisplayport SERDES clock supplyPWRG14, H13
VDDA_0P8_DSITXDSITX clock supplyPWRH15
VDDA_0P8_DSITX_CDSITX clock supplyPWRJ16
VDDA_0P8_UFSUFS analog supply lowPWRAB9
VDDA_0P8_USBUSB0-1 0.8 V analog supplyPWRAA10
VDDA_0P8_SERDES0_1SERDES0-1 analog supply lowPWRAA15, Y14, Y16
VDDA_0P8_SERDES2_3SERDES2-3 analog supply lowPWRAA12, Y11, Y13
VDDA_0P8_SERDES_C0_1SERDES0-1 clock supplyPWRAB14, AB15
VDDA_0P8_SERDES_C2_3SERDES2-3 clock supplyPWRAB12, AB13
VDDA_1P8_CSIRXCSIRX analog supply highPWRG16
VDDA_1P8_DPDisplayport SERDES analog supply highPWRH11
VDDA_1P8_DSITXDSITX analog supply highPWRJ14
VDDA_1P8_UFSUFS analog supply highPWRAC8
VDDA_1P8_USBUSB0-1 1.8 V analog supplyPWRAC9
VDDA_1P8_SERDES0_1SERDES0-1 analog supply highPWRAC14, AC15
VDDA_1P8_SERDES2_3SERDES2-3 analog supply highPWRAC11, AC12
VDDA_3P3_USBUSB0-1 3.3 V analog supplyPWRAB10
VDDA_ADC0ADC analog supply and high voltage reference (VREFP)PWRN22
VDDA_ADC1ADC analog supply and high voltage reference (VREFP)PWRM23
VDDA_0P8_PLL_DDRDDR PLL analog supplyPWRN9
VDDA_MCU_PLLGRP0Analog supply for MCU PLL Group 0PWRG18
VDDA_MCU_TEMPAnalog supply for temperature sensor 0 in MCU domainPWRP21
VDDA_1P8_MLBMLB IO supply (6-pin interface)PWRW7
VDDA_PLLGRP0Analog supply for MAIN PLL Group 0PWRY20
VDDA_PLLGRP1Analog supply for MAIN PLL Group 1PWRW17
VDDA_PLLGRP2Analog supply for MAIN PLL Group 2PWRM17
VDDA_PLLGRP3Analog supply for MAIN PLL Group 3PWRL12
VDDA_PLLGRP4Analog supply for MAIN PLL Group 4PWRR11
VDDA_PLLGRP5Analog supply for MAIN PLL Group 5 (DDR)PWRP9
VDDA_PLLGRP6Analog supply for MAIN PLL Group 6PWRW18
VDDA_0P8_PLL_MLBMLB PLL analog supplyPWRW8
VDDA_POR_WKUPWKUP domain analog supplyPWRP22
VDDA_TEMP0_1Analog supply for temperature sensor 0 and 1PWRW15
VDDA_TEMP2_3Analog supply for temperature sensor 2 and 3PWRH9
VDDA_WKUPOscillator supply for WKUP domainPWRH22
VDDSHV0IO supply for MAIN domain generalPWRU8, V7
VDDSHV0_MCUIO supply MCUSS general IO group, and MCU and MAIN domain warm reset pinsPWRL22, M22
VDDSHV1IO supply for MAIN domain IO group 1PWRAA19, AA20, AC19, AC20
VDDSHV1_MCUIO supply for MCUSS IO group 1PWRH19, H21, J20
VDDSHV2IO supply for MAIN domain IO group 2PWRAA17, AB16, AB18, AC17
VDDSHV2_MCUIO supply for MCUSS IO group 2PWRJ22, K21
VDDSHV3IO supply for MAIN domain IO group 3PWRV21, W22
VDDSHV4IO supply for MAIN domain IO group 4PWRAA21, Y22
VDDSHV5IO supply for MAIN domain IO group 5PWRT20, T22
VDDSHV6IO supply for MAIN domain IO group 6PWRU20, U22
VDDS_DDRDDR inteface power supplyPWRA1, G8, J8, K7, L8, M7, N8, P7, R8, T1
VDDS_DDR_BIASBias supply for LPDDR4PWRH7, J6, R6, T7
VDDS_DDR_CIO power for DDR Memory Clock Bit (MCB) macroPWRM9
VDDS_MMC0MMC0 IO supplyPWRAA8, AB7, Y7
VDDS_OSC1HFOSC1 supplyPWRR21
VDD_COREMAIN domain core supplyPWRJ10, K11, K13, K15, K17, K9, L10, L16, L18, M15, N14, N16, N18, P13, P15, P17, R14, R16, R18, R20, T15, T17, T9, U14, U16, U18, V15, V17, V20, W14
VDD_CPUCPU core supplyPWRN10, P11, R10, R12, U10, V11, V9, W10
VDDA_0P8_DLL_MMC0MMC0 DLL analog supplyPWRY9
VDD_MCUMCUSS core supplyPWRL20, M19, M21, N20, P19
VSSGroundGNDAA13, AC10, AC13, AD11, AD14, AD17, AE10, AE12, AE15, AE16, AE19, AE7, AF20, AF25, AF5, AG4, AG7, AH2, AH20, AH5, AJ4, AJ7, B3, B6, C1, C5, D2, D4, E1, E5, F4, G1, G7, H4, H6, K1, K4, L3, M1, M28, M4, M6, N27, N29, N3, P1, P28, P4, R3, U5A10, A13, A16, A19, A22, A7, AA11, AA14, AA16, AA18, AA7, AA9, AB17, AB19, AB20, AB22, AB8, AC16, AF11, AF14, AF17, AF8, AG10, AG13, AG16, AG19, AH11, AH14, AH17, AH8, AJ10, AJ13, AJ16, AJ19, B12, B15, B18, B21, B9, C11, C14, C17, C20, C8, D10, D13, D16, D19, D7, E12, E15, E9, F14, F8, G11, G13, G15, G17, H10, H12, H14, H16, H18, H20, H8, J11, J13, J15, J17, J21, J23, J7, J9, K10, K12, K14, K16, K18, K20, K22, K8, L13, L15, L17, L19, L21, L23, L7, L9, M10, M14, M16, M18, M20, M8, N15, N17, N19, N21, N7, P10, P12, P14, P16, P18, P20, P8, R13, R15, R17, R19, R7, R9, T10, T14, T16, T18, T21, T8, U15, U17, U19, U21, U9, V10, V12, V14, V18, V8, W11, W13, W16, W20, W9, Y10, Y12, Y15, Y17, Y19, Y21, Y8
(1) This pin must always be connected via a 1-μF capacitor to VSS.