SPRSP35J February 2019 – August 2021 DRA829J , DRA829V
Refer to the PDF data sheet for device specific package drawings
Entry into DDR Retention (Suspend-to-RAM or S2R) state is accomplished by executing a power down sequence except for the 1 device DDR supply group (VDDS_DDR_BIAS, VDDS_DDR, and VDDS_DDR_C at 1.1V), and 1 additional discrete SDRAM supply (VDD_LPDDR4_1V8 at 1.8V; not shown in diagram below) that remain energized. Exit from DDR Retention state is accomplished by executing a power up sequence with these 2 DDR supply groups remaining energized throughout the sequence. The example diagram shown is for an Isolated MCU & Main PDN type with eMMC support.