Refer to the PDF data sheet for device specific package drawings
This section describes power supply sequencing required to ensure proper device operation. The device can be operated using either an isolated or combined MCU & Main power distribution network (PDN). Two different primary power sequences are recommended based upon isolated and combined MCU & Main PDNs. In addition, the device can be operated in either MCU Only or DDR Retention low power modes. Two different desired device power supply sequences for entry and exit of low power modes are shown.
The power supply names used in this section are specific to this device and align to names given in the Signal Descriptions section. Common power supply names may be used across different devices within the Jacinto 7TM processor family. These common supply names will have very similar if not identical functions across devices.
All power sequencing timing diagrams shown will use the following terminology: