SPRSP35J February 2019 – August 2021 DRA829J , DRA829V
Refer to the PDF data sheet for device specific package drawings
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base Specification Revision 4.0, September 27, 2017.
This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal termination enabled, as described by parameter VREFCLK_TERM in Table 7-2, 4-L-PHY SERDES REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External termination should always be enabled on the source side.
|BALL NAMES in Mode 0: SERDES4_REFCLK_P, SERDES4_REFCLK_N|
|BALL NUMBERS:E8 / E7|
|VREFCLK_TERM||Single ended voltage threshold at the reference clock pin when internal termination is enabled||400||mV|
The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26, 2013.
The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3 Clause 70.
The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.
The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.