Refer to the PDF data sheet for device specific package drawings
The device contains ten multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an interface between a local host (LH), such as an Arm or a Digital Signal Processor (DSP), and any I2C-bus-compatible device that connects via the I2C serial bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface.
Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.
The WKUP_I2C0, MCU_I2C0, I2C0, and I2C1 controllers have dedicated I2C compliant open drain buffers, and support high speed mode (up to 3.4 Mbps in 1.8 V mode and up to 400 kbps in 3.3 V mode). The MCU_I2C1, I2C2, I2C3, I2C4, I2C5, and I2C6 controllers are multiplexed with standard LVCMOS I/O, connected to emulate open drain, and support fast mode (up to 400 kbps in 1.8 V/3.3 V mode). The I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1.
For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device TRM.