Refer to the PDF data sheet for device specific package drawings
Power is supplied to the Phase-Locked Loop circuitries (PLLs) by internal regulators that derive power from the off-chip power-supply.
There are total of three PLLs in the device in WKUP and MCU domains:
There are total of twenty PLLs in the device in MAIN domain:
For more information, see:
The input reference clock (OSC1_XI/OSC1_XO) is specified and the lock time is ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.