Figure 3-1 is functional block diagram for the device.
This interface is located on the
MCU Island but is available for the full system to access.
DP, SGMII, USB3.0, and PCIE[3:0]
share total of twelve SerDes lanes.
Two simultaneous flash interfaces
configured as OSPI0 and OSPI1, or HyperBus™ and OSPI1.
Figure 3-1 Functional Block Diagram