SLVSD14A June   2017  – June  2020 DRV10983-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Application Schematic
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Regulators
        1. 8.3.1.1 Step-Down Regulator
        2. 8.3.1.2 3.3-V and 1.8-V LDO
      2. 8.3.2 Protection Circuits
        1. 8.3.2.1 Thermal Shutdown
        2. 8.3.2.2 Undervoltage Lockout (UVLO)
        3. 8.3.2.3 Overcurrent Protection
        4. 8.3.2.4 Lock
      3. 8.3.3 Motor Speed Control
      4. 8.3.4 Load Dump Handling
      5. 8.3.5 Sleep or Standby Condition
        1. 8.3.5.1 Required Sequence to Enter Sleep Mode
          1. 8.3.5.1.1 Option 1
          2. 8.3.5.1.2 Option 2
      6. 8.3.6 EEPROM Access
    4. 8.4 Device Functional Modes
      1. 8.4.1  Motor Parameters
        1. 8.4.1.1 Motor Phase Resistance
        2. 8.4.1.2 BEMF Constant
      2. 8.4.2  Starting the Motor Under Different Initial Conditions
        1. 8.4.2.1 Case 1 – Motor is Stationary
        2. 8.4.2.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 8.4.2.3 Case 3 – Motor is Spinning in the Reverse Direction
      3. 8.4.3  Motor Start Sequence
        1. 8.4.3.1 Initial Speed Detect
        2. 8.4.3.2 Motor Resynchronization
        3. 8.4.3.3 Reverse Drive
        4. 8.4.3.4 Motor Brake
        5. 8.4.3.5 Motor Initialization
          1. 8.4.3.5.1 Align
          2. 8.4.3.5.2 Initial Position Detect (IPD)
            1. 8.4.3.5.2.1 IPD Operation
            2. 8.4.3.5.2.2 IPD Release Mode
            3. 8.4.3.5.2.3 IPD Advance Angle
          3. 8.4.3.5.3 Motor Start
        6. 8.4.3.6 Start-Up Timing
      4. 8.4.4  Align Current
      5. 8.4.5  Start-Up Current Setting
        1. 8.4.5.1 Start-Up Current Ramp-Up
      6. 8.4.6  Closed Loop
        1. 8.4.6.1 Half-Cycle Control and Full-Cycle Control
        2. 8.4.6.2 Analog-Mode Speed Control
        3. 8.4.6.3 Digital PWM-Input-Mode Speed Control
        4. 8.4.6.4 I2C-Mode Speed Control
        5. 8.4.6.5 Closed-Loop Accelerate
        6. 8.4.6.6 Control Coefficient
        7. 8.4.6.7 Commutation Control Advance Angle
      7. 8.4.7  Current Limit
        1. 8.4.7.1 Acceleration Current Limit
      8. 8.4.8  Lock Detect and Fault Handling
        1. 8.4.8.1 Lock0: Lock-Detection Current Limit Triggered
        2. 8.4.8.2 Lock1: Abnormal Speed
        3. 8.4.8.3 Lock2: Abnormal Kt
        4. 8.4.8.4 Lock3 (Fault3): No-Motor Fault
        5. 8.4.8.5 Lock4: Open-Loop Motor-Stuck Lock
        6. 8.4.8.6 Lock5: Closed Loop Motor Stuck Lock
      9. 8.4.9  Anti Voltage Suppression Function
        1. 8.4.9.1 Mechanical AVS Function
        2. 8.4.9.2 Inductive AVS Function
      10. 8.4.10 PWM Output
      11. 8.4.11 FG Customized Configuration
        1. 8.4.11.1 FG Output Frequency
        2. 8.4.11.2 FG Open Loop and Lock Behavior
      12. 8.4.12 Diagnostics and Visibility
        1. 8.4.12.1 Motor-Status Readback
        2. 8.4.12.2 Motor-Speed Readback
        3. 8.4.12.3 Motor Electrical-Period Readback
        4. 8.4.12.4 BEMF Constant Read Back
        5. 8.4.12.5 Motor Estimated Position by IPD
        6. 8.4.12.6 Supply-Voltage Readback
        7. 8.4.12.7 Speed-Command Readback
        8. 8.4.12.8 Speed-Command Buffer Readback
        9. 8.4.12.9 Fault Diagnostics
    5. 8.5 Register Maps
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Register Map
      3. 8.5.3 Register Descriptions
        1. 8.5.3.1  FaultReg Register (address = 0x00) [reset = 0x00]
          1. Table 11. FaultReg Register Field Descriptions
        2. 8.5.3.2  MotorSpeed Register (address = 0x01) [reset = 0x00]
          1. Table 12. MotorSpeed Register Field Descriptions
        3. 8.5.3.3  MotorPeriod Register (address = 0x02) [reset = 0x00]
          1. Table 13. MotorPeriod Register Field Descriptions
        4. 8.5.3.4  MotorKt Register (address = 0x03) [reset = 0x00]
          1. Table 14. MotorKt Register Field Descriptions
        5. 8.5.3.5  MotorCurrent Register (address = 0x04) [reset = 0x00]
          1. Table 15. MotorCurrent Register Field Descriptions
        6. 8.5.3.6  IPDPosition–SupplyVoltage Register (address = 0x05) [reset = 0x00]
          1. Table 16. IPDPosition–SupplyVoltage Register Field Descriptions
        7. 8.5.3.7  SpeedCmd–spdCmdBuffer Register (address = 0x06) [reset = 0x00]
          1. Table 17. SpeedCmd–spdCmdBuffer Register Field Descriptions
        8. 8.5.3.8  AnalogInLvl Register (address = 0x07) [reset = 0x00]
          1. Table 18. AnalogInLvl Register Field Descriptions
        9. 8.5.3.9  DeviceID–RevisionID Register (address = 0x08) [reset = 0x00]
          1. Table 19. DeviceID–RevisionID Register Field Descriptions
        10. 8.5.3.10 DeviceID–RevisionID Register (address = 0x08) [reset = 0x00]
          1. Table 20. DeviceID–RevisionID Register Field Descriptions
        11. 8.5.3.11 Unused Registers (addresses = 0x011 Through 0x2F)
        12. 8.5.3.12 SpeedCtrl Register (address = 0x30) [reset = 0x00]
          1. Table 21. SpeedCtrl Register Field Descriptions
        13. 8.5.3.13 EEPROM Programming1 Register (address = 0x31) [reset = 0x00]
          1. Table 22. EEPROM Programming1 Register Field Descriptions
        14. 8.5.3.14 EEPROM Programming2 Register (address = 0x32) [reset = 0x00]
          1. Table 23. EEPROM Programming2 Register Field Descriptions
        15. 8.5.3.15 EEPROM Programming3 Register (address = 0x33) [reset = 0x00]
          1. Table 24. EEPROM Programming3 Register Field Descriptions
        16. 8.5.3.16 EEPROM Programming4 Register (address = 0x34) [reset = 0x00]
          1. Table 25. EEPROM Programming4 Register Field Descriptions
        17. 8.5.3.17 EEPROM Programming5 Register (address = 0x35) [reset = 0x00]
          1. Table 26. EEPROM Programming5 Register Field Descriptions
        18. 8.5.3.18 EEPROM Programming6 Register (address = 0x36) [reset = 0x00]
          1. Table 27. EEPROM Programming6 Register Field Descriptions
        19. 8.5.3.19 Unused Registers (addresses = 0x37 Through 0x5F)
        20. 8.5.3.20 EECTRL Register (address = 0x60) [reset = 0x00]
          1. Table 28. EECTRL Register Field Descriptions
        21. 8.5.3.21 Unused Registers (addresses = 0x61 Through 0x8F)
        22. 8.5.3.22 CONFIG1 Register (address = 0x90) [reset = 0x00]
          1. Table 29. CONFIG1 Register Field Descriptions
        23. 8.5.3.23 CONFIG2 Register (address = 0x91) [reset = 0x00]
          1. Table 30. CONFIG2 Register Field Descriptions
        24. 8.5.3.24 CONFIG3 Register (address = 0x92) [reset = 0x00]
          1. Table 31. CONFIG3 Register Field Descriptions
        25. 8.5.3.25 CONFIG4 Register (address = 0x93) [reset = 0x00]
          1. Table 32. CONFIG4 Register Field Descriptions
        26. 8.5.3.26 CONFIG5 Register (address = 0x94) [reset = 0x00]
          1. Table 33. CONFIG5 Register Field Descriptions
        27. 8.5.3.27 CONFIG6 Register (address = 0x95) [reset = 0x00]
          1. Table 34. CONFIG6 Register Field Descriptions
        28. 8.5.3.28 CONFIG7 Register (address = 0x96) [reset = 0x00]
          1. Table 35. CONFIG7 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

over operating voltage and ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT (DRV10983Q)
IVccSLEEP1 Sleep current VSPEED = 0 V; VCC = 12 V; TA = 25℃ 48 54 µA
VSPEED = 0 V; VCC = 12 V; across temperature 81
IVcc Active current VSPEED > 0 V; buck regulator with inductor; no motor load 10 15 mA
VSPEED > 0 V; buck regulator with resistor; no motor load 13 16
SUPPLY CURRENT (DRV10983SQ)
IVccSTBY Standby current VSPEED = 0 V; buck regulator with
inductor		 8.5 14 mA
VSPEED = 0 V; buck regulator with
resistor		 11 15
IVcc Active current VSPEED > 0 V; buck regulator with
inductor; no motor load		 10 15 mA
VSPEED > 0 V; buck regulator with
resistor; no motor load		 13 16
UVLO
VUVLO_R UVLO rising threshold voltage 5.8 6 6.2 V
VUVLO_F UVLO falling threshold voltage 5.6 5.8 6 V
VUVLO_HYS UVLO threshold voltage hysteresis 170 195 220 mV
VV1P8_UVLO_R V1P8 UVLO rising threshold 1.5 1.6 1.7 V
VV1P8_UVLO_F V1P8 UVLO falling threshold 1.4 1.55 1.65 V
VV3P3_UVLO_R V3P3 UVLO rising threshold 2.7 2.85 2.95 V
VV3P3_UVLO_F V3P3 UVLO falling threshold 2.5 2.7 2.8 V
VVREG_UVLO_R VREG UVLO rising threshold 4 4.2 4.3 V
VVREG_UVLO_F VREG UVLO falling threshold 3.9 4.2 V
LDO OUTPUT
V3P3 Output voltage Buck regulator with inductor, 20-mA load 3.1 3.3 3.5 V
Buck regulator with resistor, no load
IV3P3_MAX Maximum load from V3P3 Only with inductor mode of buck operation, with resistor mode no load 20 mA
V1P8 Output voltage No load 1.7 1.8 1.9 V
STEP-DOWN REGULATOR
VREG Regulator output voltage LSW = 47 µH, CSW = 10 µF
Iload = 100 mA		 4.5 5 5.5 V
RSW = 39 Ω, CSW = 10 µF
Iload = 5 mA
IREG_MAX_L Maximum load from VREG in switching mode LSW = 47 µH, CSW = 10 µF 100 mA
IREG_MAX_R Maximum load from VREG in linear mode RSW = 39 Ω, CSW = 10 µF 5 mA
INTEGRATED MOSFET
rDS(ON) Series resistance (H + L) TA = 25˚C; V(VCC) > 6.5 V; Io = 1 A 250 400 mΩ
TA = 125˚C; V(VCC) > 6.5V; Io = 1 A 325 550
SPEED – ANALOG MODE
VAN/A_FS Analog full-speed voltage V(V3P3) × 0.9 V(V3P3) V
VAN/A_ZS Analog zero-speed voltage 0 100 mV
tSAM Sampling period for analog voltage on SPEED pin  320 µs
VAN/A_RES Analog voltage resolution 6.5 mV
SPEED – PWM DIGITAL MODE
VDIG_IH PWM input high voltage 2.2 V
VDIG_IL PWM input low voltage 0.6 V
ƒPWM PWM input frequency 0.1 100 kHz
STANDBY MODE (DRV10983SQ)
VEN_SB Analog voltage to enter standby mode  SpdCtrlMd = 0 (analog mode) 100 mV
VEX_SB Analog voltage to exit standby mode SpdCtrlMd = 0 (analog mode) 0.17 V
tEX_SB_ANA Time needed to exit from standby mode SpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SB 		1 700 ms
tEX_SB_DR_ANA Time taken to drive motor after exiting standby mode SpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SB; ISDen = 0; BrkDoneThr[2:0] = 0		 350 ms
tEX_SB_PWM Time needed to exit from standby mode SpdCtrlMd = 1 (PWM mode)
VSPEED > VDIG_IH 		2 µs
tEX_SB_DR_PWM Time taken to drive motor after exiting standby mode SpdCtrlMd = 1 (PWM mode)
VSPEED_DUTY > 0; ISDen = 0; BrkDoneThr[2:0] = 0		 350 ms
tEN_SB_ANA Time needed to enter standby mode SpdCtrlMd = 0 (analog mode)
VSPEED < VEN_SB; AvSIndEn = 0		 6 ms
tEN_SB_PWM Time needed to enter standby mode SpdCtrlMd = 1 (PMW mode)
VSPEED < VDIG_IL; AvSIndEn = 0		 60 ms
SLEEP MODE (DRV10983Q)
VEN_SL Analog voltage to enter sleep mode SpdCtrlMd = 0 (analog mode) 100 mV
VEX_SL Analog voltage to exit sleep mode SpdCtrlMd = 0 (analog mode) 2.2 V
tEX_SL_ANA Time needed to exit from sleep mode SpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SL 		2 µs
tEX_SL_DR_ANA Time taken to drive motor after exiting from sleep mode SpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SL; ISDen = 0; BrkDoneThr[2:0] = 0		 350 ms
tEX_SL_PWM Time needed to exit from sleep mode SpdCtrlMd = 1 (PWM mode)
VSPEED > VDIG_IH 		2 µs
tEX_SL_DR_PWM Time taken to drive motor after exiting from sleep mode SpdCtrlMd = 1 (PWM mode)
VSPEED > VDIG_IH; ISDen = 0; BrkDoneThr[2:0] = 0		 350 ms
tEN_SL_ANA Time needed to enter sleep mode SpdCtrlMd = 0 (analog mode)
VSPEED < VEN_SL; AvSIndEn = 0		 6 ms
tEN_SL_PWM Time needed to enter sleep mode SpdCtrlMd = 1 (PMW mode)
VSPEED < VDIG_IL; AvSIndEn = 0		 60 ms
RPD_SPEED_SL Internal SPEED pin pull down resistance to ground VSPEED = 0 (Sleep mode) 55 kΩ
DIGITAL I/O (DIR INPUT, FG OUTPUT )
VDIR_H Input high 2.2 V
VDIR_L Input low 0.6 V
VFG_OH Output high voltage Io = 5 mA 3.3 V
VFG_OL Output low voltage Io = 5 mA 0.6 V
I2C SERIAL INTERFACE
VI2C_H Input high 2.2 V
VI2C_L Input low 0.6 V
fI2C I2C clock frequency 0 400 kHz
LOCK DETECTION RELEASE TIME
tLOCK_OFF Lock release time 5 s
tLCK_ETR Lock enter time 0.3 s
OVERCURRENT PROTECTION
IOC_limit_HS HS overcurrent protection VCC < 28.5 V 3.5 4.25 5.5 A
IOC_limit_LS LS overcurrent protection VCC < 28.5 V 3.5 4.25 5.5 A
THERMAL SHUTDOWN
TSDN Junction temperature shutdown threshold 150 165 180 °C
TSDN_HYS Junction temperature shutdown hysteresis 15 20 25 °C
TWARN Junction temperature warning threshold 115 125 140 °C
PHASE DRIVER
SLPH_LH0 Phase slew rate switching low to high PHslew = 0; measure 20% to 80%;
VCC = 12 V		 85 120 145 V/µs
SLPH_LH1 Phase slew rate switching low to high PHslew = 1; measure 20% to 80%;
VCC = 12 V		 60 80 100 V/µs
SLPH_LH2 Phase slew rate switching low to high PHslew = 2; measure 20% to 80%;
VCC = 12 V		 38 50 62 V/µs
SLPH_LH3 Phase slew rate switching low to high PHslew = 3; measure 20% to 80%;
VCC = 12 V		 27 35 44 V/µs
SLPH_HL0 Phase slew rate switching high to low PHslew = 0; measure 80% to 20%;
VCC = 12 V		 85 120 145 V/µs
SLPH_HL1 Phase slew rate switching high to low PHslew = 1; measure 80% to 20%;
VCC = 12 V		 59 80 100 V/µs
SLPH_HL2 Phase slew rate switching high to low PHslew = 2; measure 80% to 20%;
VCC = 12 V		 36 50 60 V/µs
SLPH_HL3 Phase slew rate switching high to low PHslew = 3; measure 80% to 20%;
VCC = 12 V		 25 35 45 V/µs
BEMF
COMPARATOR
BEMFHYS BEMF comparator hysteresis BEMF_HYS = 0 7 20 30 mV
BEMF_HYS = 1 17 40 51
LOAD DUMP PROTECTION
VOV_R Load dump protection mode entry on rising VCC threshold 28.5 29.2 30 V
VOV_F Load dump protection mode exit on falling VCC threshold 27.7 28.2 28.8 V
VOV_HYS Load dump protection mode hysteresis 0.73 1 1.1 V
DRV10983-Q1 SLEEP_ANALOG_SLVSE89.gifFigure 1. DRV10983Q Analog Mode Timing
DRV10983-Q1 SLEEP_PWM_SLVSE89.gifFigure 2. DRV10983Q PWM Mode Timing
DRV10983-Q1 STANDBY_ANALOG_SLVSE89.gifFigure 3. DRV10983SQ Analog Mode Timing
DRV10983-Q1 STANDBY_PWM_SLVSE89.gifFigure 4. DRV10983SQ PWM Mode Timing