8.3.2.1 Auto-Resonance Engine for LRA

The DRV2625 auto-resonance engine tracks the resonant frequency of an LRA in real time, effectively locking onto the resonance frequency after half of a cycle. If the resonant frequency shifts in the middle of a waveform for any reason, the engine tracks the frequency from cycle to cycle. The auto-resonance engine accomplishes tracking by constantly monitoring the back-EMF of the actuator. Note that the auto-resonance engine is not affected by the auto calibration process, which is only used for level calibration. No calibration is required for the auto resonance engine.

8.3.2.2 Real-Time Resonance-Frequency Reporting for LRA

The smart-loop architecture makes the resonant frequency of the LRA available through I²C. Because frequency reporting occurs in real time, it must be polled while the DRV2625 device synchronizes with the LRA. The polled data should not be polled when the actuator is idle or braking.

8.3.2.3 Automatic Switch to Open-Loop for LRA

In the event that an LRA produces a non-valid back-EMF signal, the DRV2625 device automatically switches to open-loop operation and continues to deliver energy to the actuator in overdrive mode at a default and configurable frequency. If the LRA begins to produce a valid back-EMF signal, the auto-resonance engine automatically takes control and continues to track the resonant frequency in real time. When synchronized, this mode uses all of the benefits of the smart-loop architecture.

Equation 1.

The DRV2625 device offers an automatic transition to open-loop mode without the re-synchronization option. This feature is enabled by setting the LRA_AUTO_OPEN_LOOP bit. The transition to open-loop mode only occurs when the driver fails to synchronize with the LRA. The AUTO_OL_CNT[1:0] parameter can be adjusted to set the amount of non-synchronized cycles allowed before the transition to the open-loop mode. Note that the open-loop mode does not receive benefits from the smart-loop architecture, such as automatic overdrive and braking.

Equation 2.

8.3.2.4 Automatic Overdrive and Braking

A key feature of the DRV2625 is the smart-loop architecture which employs actuator feedback control for both ERMs and LRAs. The feedback control desensitizes the input waveform from the motor-response behavior by providing automatic overdrive and automatic braking.

An open-loop haptic system typically drives an overdrive voltage at startup that is higher than the steady-state rated voltage of the actuator to decrease the startup latency of the actuator. Likewise, a braking algorithm must be employed for effective braking. When using an open-loop driver, these behaviors must be contained in the input waveform data. Consider the example of an ERM actuator of Motor A and another of Motor B. The ideal input waveform in open loop is different (see Figure 16). In contrast, by using the smart-loop technology with automatic overdrive and braking, the same input waveform will work optimally for both actuators (see Figure 17). The smart-loop architecture works equally well for LRAs with a combination of feedback control and an auto-resonance engine.

Figure 16. Typical Open Loop Waveform

Figure 17. Waveform Simplification With Smart Loop

8.3.2.5 Automatic Level Calibration

The smart-loop architecture uses actuator feedback by monitoring the back-EMF behavior of the actuator. The level of back-EMF voltage can vary across actuator manufacturers because of the specific actuator construction. Auto calibration compensates for this variation and also performs scaling for the desired actuator according to the specified rated voltage and overdrive clamp-register settings. When auto calibration is performed, a 100% signal level at any of the DRV2625 input interfaces supplies the rated voltage to the actuator at steady-state. The feedback allows the output level to increase above the rated voltage level for automatic overdrive and braking, but the output level does not exceed the programmable overdrive clamp voltage.

8.3.2.6 Actuator Diagnostics

The DRV2625 device is capable of determining whether the actuator is not present (open) or shorted. If a fault is detected during the diagnostic process, the DIAG_RESULT bit is asserted.

The DRV2625 device also features actuator resistance measurement, which is available in the DIAG_Z_RESULT parameter.

Equation 3.

8.3.2.7 Automatic Re-Synchronization

For LRA actuators, the DRV2625 device features automatic re-synchronization, which automatically pushes the actuator in the correct direction when a waveform begins playing while the actuator is moving. If the actuator is at rest when the waveform begins, the DRV2625 device drives in the default direction.

8.3.3.1 Waveform Shape Selection for LRA

The DRV2625 offers a selection of either sine-wave or square-wave waveform shape in open-loop mode. The WAVE_SHAPE_LRA parameter selects which shape to use. The WAVE_SHAPE_LRA parameter is ignored in ERM mode and in closed-loop mode.

8.3.3.2 Automatic Braking in Open Loop

The DRV2625 offers automatic braking in open-loop for both ERM and LRA. To accomplish automatic braking, the DRV2625 switches to close-loop during the braking period, therefore resorting to the close-loop waveform shape. The AUTO_BRK_OL parameter can be use to enable or disable the automatic braking feature. To use the automatic braking feature, the device must be configured appropriately for closed-loop operation.

8.3.4.1 Internal Memory Interface

The DRV2625 device has two internal-ROM libraries designed by Immersion called TS2200. The first library works in closed-loop mode, and is designed for LRA actuators. The second library is specifically tuned for ERMs operated in open-loop mode. If additional adjustments are required to the library effect to optimize performance of a particular actuator model, the library parametrization parameters (ODT, SPT, SNT and BRT) can be used for fine tuning. The library selection is done by the LIB_SEL bit.

Using the internal library has several advantages including:

• Offloading processing requirements, such as digital streaming (RTP).
• Improving latency by only requiring a trigger signal.
• Reducing I²C traffic by eliminating the requirement to transfer waveform data

8.3.4.1.1 Library Parameterization

The waveforms stored in the internal library are augmented by the time offset parameters. This augmentation occurs only for the waveforms stored in the internal library and not for RTP mode. The purpose of this functionality is to add time stretching (or time shrinking) to the waveform. This functionality is useful for customizing the entire library of waveforms for a specific actuator rise time and fall time.

The time parameters that can be stretched or shrunk include:

ODT Overdrive time

SPT Sustain positive time

SNT Sustain Negative Time

BRT Brake Time

The time values are additive offsets and are 8-bit signed values. The default offset of these values is 0. Positive values add and negative values subtract from the time value of the effect that is currently played. The most positive value in the waveform is automatically interpreted as the overdrive time, and the most negative value in the waveform is automatically interpreted as the brake time. These time-offset parameters are applied to both voltage-time pairs and linear ramps. For linear ramps, linear interpolation is stretched (or shrunk) over the two operative points for the period.

Equation 4.

8.3.4.2 Real-Time Playback (RTP) Interface

The real-time playback mode is a simple, single 8-bit register interface that holds an amplitude value. When real-time playback is enabled, the RTP_INPUT parameter, which represents an amplitude value, is sent directly to the playback engine. Once triggered, the value is played until the user sends a stop trigger or removes the device from RTP mode. The RTP mode is a digital streaming mode where the user enters a register value over the I²C. Because of the similarity between RTP mode and legacy PWM modes, any API (application-programming interface) designed for use with a PWM generator in the host processor can write the data values over the I²C rather than writing the data values to the host timer. This ability frees a timer in the host while retaining compatibility with the original software.

For the LRA, the DRV2625 device automatically tracks the resonance frequency unless the CONTROL_LOOP bit is set to open loop operation. If the CONTROL_LOOP bit is set to open loop, the LRA is driven according to the open-loop frequency set in the OL_LRA_PERIOD parameter.

8.3.4.3 Process Trigger

All processes (RTP, Waveform Sequencer, Calibration and Diagnostics) in the DRV2625 device are triggered processes, which means that the user has to trigger the process before the process begins. A trigger can be achieved by software using the GO bit, or by hardware using the TRIG/INTZ pin. The process stops once it finishes, or if a stop trigger is sent. For information on external trigger functionality refer to Multi-Purpose Pin Functionality.

A typical process (either RTP, Waveform Sequencer, Calibration or Diagnostics) will start and end follwing the diagram in Figure 18.

Figure 18. Typical Process Execution

8.3.12.1 Thermal Sensor

The DRV2625 has a thermal circuit that immediately puts the device in standby state and sets the OVER_TEMP bit in the event of an over-temperature condition.

If the interrupt functionality is selected in the TRIG_PIN_FUNC parameter and the interrupt is not masked, and interrupt will be fired to alert the host processor of a critical condition.

8.3.12.2 Over-Current Protection

During waveform playback, if the impedance at the output pin of the DRV2625 device is too low, the DRV2625 device immediately goes into standby state and latches the over-current flag (OC_DETECT bit).

If the interrupt functionality is selected in the TRIG_PIN_FUNC parameter and the interrupt is not masked, an interrupt will be fired to alert the host processor of a critical condition.

8.3.12.3 VDD UVLO Protection

The DRV2625 device has a battery monitor that monitors the VDD level to ensure that is above a configurable threshold (using UVLO_THRES[2:0] parameter).

In the event of a VDD droop, the DRV2625 device immediately goes into standby state to reduce current consumption and latches the UVLO flag (UVLO bit).

If the interrupt functionality is selected in the TRIG_PIN_FUNC parameter and the interrupt is not masked, and interrupt will be fired to alert the host processor of a critical condition.

8.3.12.4 Brownout Protection

The DRV2625 device has on-chip brownout protection. When activated, a reset signal is issued that returns the DRV2625 device to the initial default state. If the regulator voltage V_(REG) goes below the brownout protection threshold (V_(BOT)) the DRV2625 device automatically shuts down. When V_(REG) returns to the typical output voltage (1.8 V) the DRV2625 device returns to the initial device state. The brownout protection threshold (V_(BOT)) is typically at 1.6 V.

8.3.16.1 Trigger-Pulse Functionality

The trigger-pulse functionality allows for an external processor to initiate the process (either waveform sequencer, RTP, diagnostics or calibration) by pulsing the TRIG/INTZ pin. The process will initiate and play until it is done, at which point it will go back into standby mode to preserve power. If a stop trigger (another trigger-pulse) is received before the routine has finished, the routine will stop and the device will go back into standby state. In the case of diagnostics mode, a stop trigger causes the diagnostic routine to abort and no result will be reported. In the case of automatic level calibration routine, a stop trigger will cause the calibration to abort unless the AUTO_CAL_TIME[2:0] is set to trigger control, in which case the stop trigger is required for the calibration to complete, and the calibration will graciously finish and provide the expected output. Also note that a stop trigger can also be achieved by writing 0 to the GO bit.

The minimum pulse width duration is 1 µs.

Figure 19. TRIG/INTZ Functionality in Trigger-Pulse Mode

8.3.16.2 Trigger-Level (Enable) Functionality

The trigger-level (enable) functionality allows for an external micro-controller to wake up the DRV2625 by asserting the TRIG/INTZ pin (high), which immediately starts playing the process (either waveform sequencer, RTP value, diagnostics or auto-calibration). Once the TRIG/INTZ pin de-asserts (low) the device goes back to standby state to preserve power. If braking is desired before going into standby state, the AUTO_BRK_INTO_STBY bit can be set to allow automatic braking. Note that automatic braking is ignored during calibration.

Figure 20. TRIG/INTZ Functionality in Trigger-Level (Enable) Mode

8.3.16.3 Interrupt Functionality

The interrupt functionality allows for the DRV2625 to communicate to an external processor that a particular condition has occurred. When configured as an interrupt, the TRIG/INTZ pin becomes an output in open-drain configuration. An external pull-up is required for this mode. When asserted, the TRIG/INTZ pin will pull down the node until the interrupt is cleared (which is done by a reading the status register). All interrupts are maskable. A description of the supported interrupts is as follows:

OC_DETECT is flagged if an over-current event happens in the output stage during a process execution (such as waveform playback or auto-calibration).

OVER_TEMP is flagged if the junction temperature goes above the thermal threshold during a process execution (such as waveform playback, diagnostics or auto-calibration).

UVLO is flagged if VDD drops below the VDD_THRES voltage during a process execution (such as waveform playback, diagnostics or auto-calibration).

PROCESS_DONE is flagged when the process (waveform sequencer, diagnostics or calibration) finishes. The PROCESS_DONE bit does not assert if the process is interrupted (such as with a stop trigger or by a critical condition). Note that RTP will never cause the PROCESS_DONE to assert because RTP never finishes on its own.

PRG_ERROR is flagged if the data read in the RAM is corrupted.

Figure 21. TRIG/INTZ Functionality in Interrupt Mode

Critical conditions, such as UVLO, over-temperature or over-current will not be monitored while the device is in standby state. However, UVLO and over-temperature conditions will be monitored during I²C communication is ongoing, even if the device is in standby state.

8.6.1.1 Drive-Time Programming

The resonance frequency of each LRA actuator varies based on many factors and is generally dominated by mechanical properties. The auto-resonance engine-tracking system is optimized by providing information about the resonance frequency of the actuator. The DRIVE_TIME[4:0] bit is used as an initial guess for the half-period of the LRA. The drive time is automatically and quickly adjusted for optimum drive. For example, if the LRA has a resonance frequency of 200 Hz, then the drive time should be set to 2.5 ms.

For ERM actuators, the DRIVE_TIME[4:0] bit controls the rate for back-EMF sampling. Lower drive times imply higher back-EMF sampling frequencies which cause higher peak-to-average ratios in the output signal, and requires more supply headroom. Higher drive times imply lower back-EMF sampling frequencies which cause the feedback to react at a slower rate.

8.6.1.2 Current-Dissipation Time Programming

To sense the back-EMF of the actuator, the DRV2625 device goes into high impedance mode. However, before the device enters this mode, the device must dissipate the current in the actuator. The DRV2625 device controls the time allocated for dissipation-current through the IDISS_TIME[3:0] parameter.

8.6.1.3 Blanking Time Programming

After the current in the actuator dissipates, the DRV2625 device waits for a blanking time of the signal to settle before the back-EMF analog-to-digital (AD) conversion converts. The BLANKING_TIME[3:0] parameter controls this time.

8.6.1.4 Zero-Crossing Detect-Time Programming

When the blanking time expires, the back-EMF AD monitors for zero crossings. The ZC_DET_TIME[1:0] parameter controls the minimum time allowed for detecting zero crossings.

8.6.2.1 Rated Voltage Programming

The rated voltage is the driving voltage that the driver will output during steady state. However, in closed-loop drive mode, temporarily having an output voltage that is higher than the rated voltage is possible.

The RATED_VOLTAGE[7:0] parameter sets the rated voltage for the closed-loop drive modes.

Equation 5.

Equation 6.

In open-loop mode, the RATED_VOLTAGE[7:0] parameter is ignored. Instead, the OD_CLAMP[7:0] parameter is used to set the full-scale voltage for the open-loop drive modes.

Equation 7.

Equation 8.

The auto-calibration routine uses the RATED_VOLTAGE[7:0] and OD_CLAMP[7:0] bits as inputs and therefore these registers must be written before calibration is performed. Any modification of this register value should be followed by calibration to appropriately set A_CAL_BEMF[7:0].

8.6.2.2 Overdrive Voltage-Clamp Programming

During closed-loop operation, the actuator feedback allows the output voltage to go above the rated voltage during the automatic overdrive and automatic braking periods. The OD_CLAMP[7:0] parameter sets a clamp so that the automatic overdrive is bounded. The OD_CLAMP[7:0] parameter also serves as the full-scale reference voltage for open-loop operation. The OD_CLAMP[7:0] parameter always represents the maximum peak voltage that is allowed, regardless of the mode.

Equation 9.

Equation 10.

8.6.3.1 TI Haptic Broadcast Mode

The DRV2625 device has a TI haptic broadcast mode where, if enabled using the I²C_BCAST_EN bit, will make the device respond to the slave address 0x58 (7-bit) or 1011000 in binary. This mode is useful in the event that multiple haptic drivers implementing the TI haptic broadcast mode as installed in the system. In such a scenario, writing the GO bit to the 0x58 slave address will cause all haptic drivers to trigger the process at the same time.

8.6.3.2 I²C Communication Availability

The I²C protocol is available for read/write operations during Standby, and Active states.

8.6.3.3 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 23 shows a typical sequence. The master device generates the 7-bit slave address and the read-write (R/W) bit to start communication with a slave device. The master device then waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge clock period to indicate acknowledgment. When the acknowledgment occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection.

The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word transfers, the master generates a stop condition to release the bus. Figure 23 shows a generic data-transfer sequence.

Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Pull-up resistors between 660 O and 4.7 kO are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2625 supply voltage, V_DD.

Figure 23. Typical I²C Sequence

The DRV2625 device operates as an I²C-slave 1.8-V logic thresholds, but can operate up to the V_DD voltage. The device address is 0x5A (7-bit), or 1011010 in binary which is equivalent to 0xB4 (8-bit) for writing and 0xB5 (8-bit) for reading.

8.6.3.4 Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte R/W operations for all registers.

During multiple-byte read operations, the DRV2625 device responds with data one byte at a time and beginning at the signed register. The device responds as long as the master device continues to respond with acknowledges.

The DRV2625 supports sequential I²C addressing. For write transactions, a sequential I²C write transaction has taken place if a register is issued followed by data for that register as well as the remaining registers that follow. For I²C sequential-write transactions, the register issued then serves as the starting point and the amount of data transmitted subsequently before a stop or start is transmitted determines how many registers are written.

8.6.3.5 Single-Byte Write

As shown in Figure 24, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read-write bit. The read-write bit determines the direction of the data transfer. For a write-data transfer, the read-write bit must be set to 0. After receiving the correct I²C device address and the read-write bit, the DRV2625 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the DRV2625 internal-memory address that is accessed. After receiving the register byte, the device responds again with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 24. Single-Byte Write Transfer

8.6.3.6 Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DRV2625 device as shown in Figure 25. After receiving each data byte, the DRV2625 device responds with an acknowledge bit.

Figure 25. Multiple-Byte Write Transfer

8.6.3.7 Single-Byte Read

Figure 26 shows that a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I²C device address and the read-write bit. For the data-read transfer, both a write followed by a read actually occur. Initially, a write occurs to transfer the address byte of the internal memory address to be read. As a result, the read-write bit is set to 0.

After receiving the DRV2625 address and the read-write bit, the DRV2625 device responds with an acknowledge bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit. The master device transmits another start condition followed by the DRV2625 address and the read-write bit again. On this occasion, the read-write bit is set to 1, indicating a read transfer. Next, the DRV2625 device transmits the data byte from the memory address that is read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer. See the note in the General I2C Operation section.

Figure 26. Single-Byte Read Transfer

8.6.3.8 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the DRV2625 device to the master device as shown in Figure 27. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 27. Multiple-Byte Read Transfer

8.6.4.1 Programming for ERM Open-Loop Operation

To configure the DRV2625 device in ERM open-loop operation, the ERM must be selected by writing the LRA_ERM bit to 1, and the CONTROL_LOOP bit to 1.

8.6.4.2 Programming for LRA Open-Loop Operation

To configure the DRV2625 device in LRA open-loop operation, the LRA must be selected by writing the LRA_ERM bit to 0, and the CONTROL_LOOP bit to 1. Additionally, the OL_LRA_PERIOD parameter must be configured with the appropriate LRA frequency.

Table 2. Calibration Routine Behavior Under Different AUTO_CAL_TIME Selections

8.6.8.1 Data Formats for Waveform Playback

The DRV2625 uses a signed data format (2's complement) to specify the magnitude and direction of the drive. The actuator can be driven in either closed-loop or open-loop. In closed-loop, positive numbers indicate the magnitude of the drive desired. Negative numbers are interpreted as a brake signal, which is automatic in closed-loop. In open-loop, positive and negative numbers are required to specify amplitude magnitude for both driving and braking. In the case that automatic braking is selected for open loop, then any negative number will be interpreted as a brake signal.

8.6.8.2 Open-Loop Mode

In open-loop mode, the reference level for full-scale drive is set by the OD_CLAMP[7:0] parameter. A mid-scale input value gives no drive signal, and a less-than mid-scale gives a negative drive value. For an ERM, a negative drive value results in counter-rotation, or braking. For an LRA, a negative drive value results in a 180-degree phase shift in commutation.

8.6.8.3 Closed-Loop Mode

In closed-loop mode, the DRV2625 device provides automatic overdrive and braking for both ERM and LRA devices. Positive values indicate that acceleration is desired. Negative values and 0 indicate that braking is desired.

The reference level for steady-state full-scale drive is set by the RATED_VOLTAGE[7:0] bit (when auto-calibration is performed). The output voltage can momentarily exceed the rated voltage for automatic overdrive and braking, but does not exceed the OD_CLAMP[7:0] voltage. Braking occurs automatically based on the input signal when the back-EMF feedback determines that braking is necessary.

In the event that the user is concerned that the overdrive time may be too high for a particular actuator, the OD_CLAMP_TIME[1:0] can be used to limit the amount of time spent in over-drive mode (a voltage above the rated voltage). If the overdrive time is exceeded and the DRV2625 device is still attempting to overdrive the actuator, a new clamp is enforced, which is specified in the RATED_VOLTAGE_CLAMP[7:0] parameter, which is enforced until a brake signal is received. During braking, the device will be allowed to overdrive for the time specified in the OD_CLAMP_TIME[1:0], and, if exceeded, the RATED_VOLTAGE_CLAMP[7:0] is enforced. This feature ensures that the actuator will not be overdriven continuously for longer than desired.

8.6.9.1 Waveform Playback Using RTP Mode

The user can enter the RTP mode by writing to the MODE[1:0] parameter. In RTP mode, when the DRV2625 device received a trigger, the device drives the actuator continuously with the amplitude specified in the RTP_INPUT[7:0] parameter. Because the amplitude tracks the value specified in the RTP_INPUT[7:0] parameter, the I²C bus can stream waveforms. To stop driving the user can either change modes or send a stop trigger (either write 0 to the GO bit or using the external trigger).

8.6.9.2 Waveform Sequencer

To play haptic effects from the internal memory, the effects must first be loaded into the waveform sequencer, and then the effects can be launched by using any of the trigger options.

The waveform sequencer queues waveform-library identifiers for playback. Eight sequence registers queue up to eight library waveforms for sequential playback. A waveform identifier is an integer value referring to the index position of a waveform in the internal memory. Playback begins at WAV_FRM_SEQ1 when the user triggers the waveform sequencer. When playback of that waveform ends, the waveform sequencer plays the next waveform identifier held in WAV_FRM_SEQ2 (if non-zero). The waveform sequencer continues in this way until the sequencer reaches an identifier value of zero or until all eight identifiers are played whichever comes first.

The waveform identifier is a 7-bit number. The MSB of each sequence register can be used to implement a delay between sequence waveforms. When the MSB is high, bits 6-0 indicate the length of the wait time. The wait time for that step then becomes WAV_FRM_SEQ[6:0] × 10 ms.

The DRV2625 device allows for looping of individual waveforms by using the WAVn_SEQ_LOOP parameters. When used, the state machine will loop the particular waveform the number of times specified in the associated WAVn_SEQ_LOOP parameter before moving to the next waveform. Additionally, the entire sequencer of waveforms can be looped a number of times specified by the WAV_SEQ_MAIN_LOOP parameter. The waveform-looping feature is useful for long, custom haptic playbacks, such as a haptic ringtone.

Figure 29. Waveform Sequencer Programming

8.6.9.3 Waveform Playback Triggers

The DRV2625 device has 2 modes of waveform playback: Waveform Sequencer and RTP. Both modes can be triggered externally by using the TRIG/INTZ pin or internally by using the GO bit. If using external trigger, the TRIG_PIN_FUNC most be selected appropriately.

8.6.9.3.1 Playback Trigger Without Automatic Brake into Standby

When automatic braking into standby is disabled (AUTO_BRK_INTO_STBY bit set to 0), playback can be triggered in both RTP and waveform sequencer modes with internal trigger by writing a 1 to the GO bit, and stopped by writing a 0 to the GO bit. Playback can also be triggered by the external trigger by following the trigger-pulse or trigger-level specifications (see Figure 19 and Figure 20 for details). Note that internal trigger is not available if the external trigger pin is set to trigger-level (TRIG_PIN_FUNC = 1)

RTP playback (MODE[1:0] = 0), once triggered, will run indefinitely until the waveform is stopped. The waveform sequencer (MODE[1:0] = 1) will run until it reaches the end point and will automatically go into standby without a cancel trigger being received, unless an infinite loop is requested.

8.6.9.3.1.1 Playback Trigger With Automatic Brake into Standby (SimpleDrive)

If automatic braking into standby is enabled (AUTO_BRK_INTO_STBY bit is set to 1), then the device part will go into brake mode before going into standby. This feature introduces new timing requirements that are described in below diagrams.

Figure 30. Waveform Sequencer with Trigger-Pulse

Figure 32. Waveform Sequencer with Trigger-Level Behavior when TRIG/INTZ Pin Left High

Figure 34. Playback Start and stop Trigger (Pulse) (RTP or Waveform Sequencer)

Figure 36. Playback Start and stop Trigger (Internal GO bit) (RTP or Waveform Sequencer)

Figure 38. Trigger-Pulse and Delayed Start (RTP or Waveform Sequencer)

Figure 40. GO bit Trigger with Delayed Start (RTP or Waveform Sequencer)

Figure 31. Waveform Sequencer with Trigger-Level

Figure 33. Fast Start Stop with Trigger-Pulse (RTP or Waveform Sequencer)

Figure 35. Playback Start and stop Trigger (Level)(RTP or Waveform Sequencer)

Figure 37. Trigger-Level with Delayed Start (RTP or Waveform Sequencer)

Figure 39. Trigger-Pulse and Delayed Start with Ignored Pulse (RTP or Waveform Sequencer)

Figure 41. Trigger-Pulse Behavior when TRIG/INTZ Pin Left High (RTP or Waveform Sequencer)

Table 4. Address: 0x00

Table 5. Address: 0x01

Table 6. Address: 0x02

Table 7. Address: 0x03

Table 8. Address: 0x04

Table 9. Address: 0x05

Table 10. Address: 0x06

Table 11. Address: 0x07

Table 12. Address: 0x08

Table 13. Address: 0x09

Table 14. Address: 0x0A

Table 15. Address: 0x0B

Table 16. Address: 0x0C

Table 17. Address: 0x0D

Table 18. Address: 0x0E

Table 19. Address: 0x0F

Table 20. Address: 0x10

Table 21. Address: 0x11

Table 22. Address: 0x12

Table 23. Address: 0x13

Table 24. Address: 0x14

Table 25. Address: 0x15

Table 26. Address: 0x16

Table 27. Address: 0x17

Table 28. Address: 0x18

Table 29. Address: 0x19

Table 30. Address: 0x1A

Table 31. Address: 0x1B

Table 32. Address: 0x1C

Table 33. Address: 0x1D

Table 34. Address: 0x1F

Table 35. Address: 0x20

Table 36. Address: 0x21

Table 37. Address: 0x22

Table 38. Address: 0x23

Table 39. Address: 0x24

Table 40. Address: 0x25

Table 41. Address: 0x26

Table 42. Address: 0x27

Table 43. Address: 0x28

Table 44. Address: 0x29

Table 45. Address: 0x2A

Table 46. Address: 0x2C

Table 47. Address: 0x2E

Table 48. Address: 0x2F

Table 49. Address: 0x30