SLOS751D March   2013  – November 2018 DRV2667

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Support for Haptic Piezo Actuators
      2. 7.3.2  Flexible Front End Interface
      3. 7.3.3  Ramp Down Behavior
      4. 7.3.4  Low Latency Startup
      5. 7.3.5  Low Power Standby Mode
      6. 7.3.6  Device Reset
      7. 7.3.7  Amplifier Gain
      8. 7.3.8  Adjustable Boost Voltage
      9. 7.3.9  Adjustable Current Limit
      10. 7.3.10 Internal Charge Pump
      11. 7.3.11 Device Protection
        1. 7.3.11.1 Thermal Protection
        2. 7.3.11.2 Overcurrent Protection
        3. 7.3.11.3 Brownout Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 FIFO Mode
        1. 7.4.1.1 Waveform Timeout
      2. 7.4.2 Direct Playback from RAM Mode
      3. 7.4.3 Waveform Synthesis Playback Mode
      4. 7.4.4 Waveform Sequencer
      5. 7.4.5 Analog Playback Mode
      6. 7.4.6 Low Voltage Operation Mode
    5. 7.5 Programming
      1. 7.5.1 Programming the Boost Voltage
      2. 7.5.2 Programming the Boost Current Limit
      3. 7.5.3 Programming the RAM
        1. 7.5.3.1 Accessing the RAM
        2. 7.5.3.2 RAM Format
          1. 7.5.3.2.1 Programming the Waveform Sequencer
      4. 7.5.4 I2C Interface
        1. 7.5.4.1 General I2C Operation
        2. 7.5.4.2 Single-Byte and Multiple-Byte Transfers
        3. 7.5.4.3 Single-Byte Write
        4. 7.5.4.4 Multiple-Byte Write and Incremental Multiple-Byte Write
        5. 7.5.4.5 Single-Byte Read
        6. 7.5.4.6 Multiple-Byte Read
    6. 7.6 Register Map
      1. 7.6.1  Address: 0x00
        1. Table 5. Address: 0x00
      2. 7.6.2  Address: 0x01
        1. Table 6. Address: 0x01
      3. 7.6.3  Address: 0x02
        1. Table 7. Address: 0x02
      4. 7.6.4  Address: 0x03
        1. Table 8. Address: 0x03
      5. 7.6.5  Address: 0x04
        1. Table 9. Address: 0x04
      6. 7.6.6  Address: 0x05
        1. Table 10. Address: 0x05
      7. 7.6.7  Address: 0x06
        1. Table 11. Address: 0x06
      8. 7.6.8  Address: 0x07
        1. Table 12. Address: 0x07
      9. 7.6.9  Address: 0x08
        1. Table 13. Address: 0x08
      10. 7.6.10 Address: 0x09
        1. Table 14. Address: 0x09
      11. 7.6.11 Address: 0x0A
        1. Table 15. Address: 0x0A
      12. 7.6.12 Address: 0x0B
        1. Table 16. Address: 0x0B
      13. 7.6.13 Address: 0xFF
        1. Table 17. Address: 0xFF
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Piezo Actuator Selection
        3. 8.2.2.3 Boost Capacitor Selection
        4. 8.2.2.4 Bulk Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 Initialization Procedure
      2. 8.3.2 Typical Usage Examples
        1. 8.3.2.1 Single Click or Alert Example
        2. 8.3.2.2 Library Storage Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

TA = 25 °C, VDD = 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG Voltage at the REG pin 1.6 1.75 1.9 V
IIL Digital low-level input current SDA, SCL
VDD = 3.6 V, VI = 0 V
1 µA
IIH Digital high-level input current SDA, SCL
VDD = 3.6 V, VI = VDD
1 uA
VIL Digital low-level input voltage SDA, SCL
VDD = 3.6 V
0.5 V
VIH Digital high-level input voltage SDA, SCL
VDD = 3.6 V
1.4 V
VOL Digital low-level output voltage SDA
3-mA sink current
0.4 V
ISD Shutdown current VDD = 3.6 V, STANDBY = 1 10 µA
IQ Quiescent current Digital mode VDD = 3.6 V, STANDBY = 0 130 175 µA
Analog mode VDD = 3.6 V, analog input mode,
VBST = 105 V
24 mA
VDD = 3.6 V, analog input mode,
VBST = 80 V
13
VDD = 3.6 V, analog input mode,
VBST = 50 V
9
VDD = 3.6 V, analog input mode,
VBST = 30 V
5
RIN Input impedance IN+, IN–; All gains 100
VOUT(FS) Full-scale output voltage (digital mode) GAIN[1:0] = 00 49 50 51 VPP
GAIN[1:0] = 01 98 100 102
GAIN[1:0] = 10 147 150 153
GAIN[1:0] = 01 196 200 204
VOUT(OS) Output offset All gains –0.25 0.25 V
BW Amplifier bandwidth GAIN[1:0] = 00, VOUT = 50 VPP,
no load
20 kHz
GAIN[1:0] = 01, VOUT = 100 VPP,
no load
10
GAIN[1:0] = 10, VOUT = 150 VPP,
no load
7.5
GAIN[1:0] = 11, VOUT = 200 VPP,
no load
5
IBAT, AVG Average battery current during operation CL = 220 nF, f = 200 Hz, VBST = 30 V, GAIN[1:0] = 00, VOUT = 50 VPP 69 mA
CL = 680 nF, f = 150 Hz, VBST = 30 V, GAIN[1:0] = 00, VOUT = 50 VPP 75
CL = 680 nF, f = 300 Hz, VBST = 30 V, GAIN[1:0] = 00, VOUT = 50 VPP 115
CL = 22 nF, f = 200 Hz, VBST = 80 V, GAIN[1:0] = 10, VOUT = 150 VPP 67
CL = 47 nF, f = 150 Hz, VBST = 105 V, GAIN[1:0] = 11, VOUT = 200 VPP 210
CL = 47 nF, f = 300 Hz, VBST = 105 V, GAIN[1:0] = 11, VOUT = 200 VPP 400
THD+N Total harmonic distortion plus noise f = 300 Hz, VOUT = 200 VPP 1%
fS Output sample rate Digital playback engine sample rate 7.8 8 8.05 kHz