SLOS751D March   2013  – November 2018 DRV2667

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Support for Haptic Piezo Actuators
      2. 7.3.2  Flexible Front End Interface
      3. 7.3.3  Ramp Down Behavior
      4. 7.3.4  Low Latency Startup
      5. 7.3.5  Low Power Standby Mode
      6. 7.3.6  Device Reset
      7. 7.3.7  Amplifier Gain
      8. 7.3.8  Adjustable Boost Voltage
      9. 7.3.9  Adjustable Current Limit
      10. 7.3.10 Internal Charge Pump
      11. 7.3.11 Device Protection
        1. 7.3.11.1 Thermal Protection
        2. 7.3.11.2 Overcurrent Protection
        3. 7.3.11.3 Brownout Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 FIFO Mode
        1. 7.4.1.1 Waveform Timeout
      2. 7.4.2 Direct Playback from RAM Mode
      3. 7.4.3 Waveform Synthesis Playback Mode
      4. 7.4.4 Waveform Sequencer
      5. 7.4.5 Analog Playback Mode
      6. 7.4.6 Low Voltage Operation Mode
    5. 7.5 Programming
      1. 7.5.1 Programming the Boost Voltage
      2. 7.5.2 Programming the Boost Current Limit
      3. 7.5.3 Programming the RAM
        1. 7.5.3.1 Accessing the RAM
        2. 7.5.3.2 RAM Format
          1. 7.5.3.2.1 Programming the Waveform Sequencer
      4. 7.5.4 I2C Interface
        1. 7.5.4.1 General I2C Operation
        2. 7.5.4.2 Single-Byte and Multiple-Byte Transfers
        3. 7.5.4.3 Single-Byte Write
        4. 7.5.4.4 Multiple-Byte Write and Incremental Multiple-Byte Write
        5. 7.5.4.5 Single-Byte Read
        6. 7.5.4.6 Multiple-Byte Read
    6. 7.6 Register Map
      1. 7.6.1  Address: 0x00
        1. Table 5. Address: 0x00
      2. 7.6.2  Address: 0x01
        1. Table 6. Address: 0x01
      3. 7.6.3  Address: 0x02
        1. Table 7. Address: 0x02
      4. 7.6.4  Address: 0x03
        1. Table 8. Address: 0x03
      5. 7.6.5  Address: 0x04
        1. Table 9. Address: 0x04
      6. 7.6.6  Address: 0x05
        1. Table 10. Address: 0x05
      7. 7.6.7  Address: 0x06
        1. Table 11. Address: 0x06
      8. 7.6.8  Address: 0x07
        1. Table 12. Address: 0x07
      9. 7.6.9  Address: 0x08
        1. Table 13. Address: 0x08
      10. 7.6.10 Address: 0x09
        1. Table 14. Address: 0x09
      11. 7.6.11 Address: 0x0A
        1. Table 15. Address: 0x0A
      12. 7.6.12 Address: 0x0B
        1. Table 16. Address: 0x0B
      13. 7.6.13 Address: 0xFF
        1. Table 17. Address: 0xFF
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Piezo Actuator Selection
        3. 8.2.2.3 Boost Capacitor Selection
        4. 8.2.2.4 Bulk Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Setup
      1. 8.3.1 Initialization Procedure
      2. 8.3.2 Typical Usage Examples
        1. 8.3.2.1 Single Click or Alert Example
        2. 8.3.2.2 Library Storage Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

RAM Format

The RAM is structured into 3 main blocks as shown in Figure 25:

  • Header size block; 1 byte
  • Header block; N x 5 bytes, where N is the number of effects stored
  • Waveform data block
DRV2667 memory_map_slos905.gifFigure 25. RAM Structure

The first byte of the RAM (at memory location 0x00 on Page 1) must contain the header size. The header size refers to the last byte in the header, so the value stored must be N x 5 + 1, as shown in Figure 25.

The header block describes the location of the waveform data content. The structure of the header consists of 5-byte blocks containing the following information (see Figure 26):

  • Start address, upper byte
  • Start address, lower byte
  • Stop address, upper byte
  • Stop address, lower byte
  • Repeat count
DRV2667 header_format_slos905.gifFigure 26. Header Format

Because more than 8-bits are required to address the 2 kB of memory, each start and stop address consists of two bytes. The start address contains the location of the first byte in the waveform and the stop byte contains the locations of the last byte in the waveform. Within the address byte, the upper byte contains the page address, and the lower byte refers to the specified address within the page (see Figure 27). The upper byte interprets a 0 as Page 1, and a 7 as Page 8 because the waveform processing engine cannot access the control space in Page 0.

DRV2667 address_bytes_slos905.gifFigure 27. Header Address Byte Format

The repeat count byte contains the number of times this waveform identifier (which starts at the start address and ends at the stop address) is to be repeated when it is called during playback. A 0 in this byte is interpreted as an infinite loop and the waveform is played indefinitely until the GO bit is cleared by the user. Otherwise, the repeat count is simply the number of times that the waveform is repeated.

The waveform data can be interpreted in two ways:

  • Direct Playback from RAM mode
  • Waveform Synthesis Playback mode

Note that both modes can be stored in the RAM, and the device interprets the waveform data according to the mode specified. To signal the device which mode is desired, the MSB of the start address, upper byte is used (see Figure 27). A 0 indicates Direct Playback from RAM Mode, and a 1 indicates a Waveform Synthesis Playback Mode.

The Direct Playback from RAM mode requires no special handling: the waveform starts at the start-address location and plays each sub-sequent byte at the Nyquist-rate. The data is stored in twos complement, where 0xFF is interpreted as full-scale, 0x00 is no signal, and 0x80 is negative full-scale. The waveform is played at an 8-kHz data rate.

The Waveform Synthesis Playback Mode stores data in sinusoidal chunks, where each chunk consists of four bytes as shown in Figure 28:

  • Amplitude
  • Frequency
  • Number of Cycles (Duration)
  • Envelope
DRV2667 waveform_synth_mem_struct_slos905.gifFigure 28. Waveform Synthesizer Format

The interpretation of each of these four bytes is outlined in Table 3.

Table 3. Waveform Chunk Bytes for Synthesizer

BYTE NAME DESCRIPTION
1 Amplitude

The amplitude byte refers to the magnitude of the synthesized sinusoid. 0xFF produces a full-scale sinusoid, 0x80 produces a half-scale sinusoid, and 0x00 does not produce any signal. An amplitude of 0x00 can be useful for producing timed waits or delays within the effect.

To calculate the absolute peak voltage, use the following equation, where amplitude is a single-byte integer:

Peak voltage = amplitude / 255 x full-scale peak voltage

2 Frequency

The frequency byte adjusts the frequency of the synthesized sinusoid. The minimum frequency is 7.8125 Hz. A value of zero is not allowed. The sinusoidal frequency is determined with the following equation, where frequency is a single-byte integer:

Sinusoid frequency (Hz) = 7.8125 x frequency

3 Number of Cycles (Duration)

The number of sinusoidal cycles to be played by the synthesizer. A convenient way to specify the duration of a coherent sinusoid is by inputting the number of cycles. This method ensures that the waveform chunk will always begin and end at zero amplitude, thus avoiding discontinuities. The actual duration in time given by this value may be calculated through the following equation, where # of cycles and frequency are both single-byte integers.

Duration (ms) = 1000 x # of cycles / (7.8125 x frequency)

4 Envelope The envelope byte is divided into two nibbles. The upper nibble, bits [7:4], sets the ramp-up rate at the beginning of the synthesized sinusoid, and the lower nibble, bits [3:0], sets the ramp-down rate at the end of the synthesized sinusoid. The user must note that the ramp-up time is included in the duration parameter of the waveform, and the ramp-down time is appended to the duration parameter of the waveform. As such, if a ramp-up time is used, the ramp-up time must be less than the duration time as programmed in byte 3. Also note that the Total Ramp Time is for a ramp to full-scale amplitude (amplitude = 0xFF). Ramps to a fraction of full-scale have the same fraction of the Total Ramp Time.
Nibble Value Total Ramp Time
0 No Envelope
1 32 ms
2 64 ms
3 96 ms
4 128 ms
5 160 ms
6 192 ms
7 224 ms
8 256 ms
9 512 ms
10 768 ms
11 1024 ms
12 1280 ms
13 1536 ms
14 1792 ms
15 2048 ms