SLOS751D March 2013 – November 2018 DRV2667
The DRV2667 device has a timeout period after the FIFO has emptied. This timeout period allows the user time to send a subsequent waveform before the device logic puts the device into idle mode, that then allows the host processor time to cue up an adjoining waveform from memory. After the timeout expires, the DRV2667 device must re-enter the 2 ms startup sequence before the next waveform plays. The timeout period is register-selectable to be 5, 10, 15 or 20 ms.