SLOS861B March   2015  – April 2015 DRV2700

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Boost + Amplifier Configuration
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Boost Converter and Control Loop
      2. 8.3.2 High-Voltage Amplifier
      3. 8.3.3 Fast Start-Up (Enable Pin)
      4. 8.3.4 Gain Control
      5. 8.3.5 Adjustable Boost Voltage
      6. 8.3.6 Adjustable Boost Current-Limit
      7. 8.3.7 Internal Charge Pump
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boost + Amplifier Mode
      2. 8.4.2 Flyback Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 AC-Coupled DAC Input Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Piezo Load Selection
          2. 9.2.1.2.2  Programming The Boost Voltage
          3. 9.2.1.2.3  Inductor and Transformer Selection
          4. 9.2.1.2.4  Programing the Boost and Flyback Current-Limit
          5. 9.2.1.2.5  Boost Capacitor Selection
          6. 9.2.1.2.6  Pulldown FET and Resistors
          7. 9.2.1.2.7  Low-Voltage Operation
          8. 9.2.1.2.8  Current Consumption Calculation
          9. 9.2.1.2.9  Input Filter Considerations
          10. 9.2.1.2.10 Output Limiting Factors
          11. 9.2.1.2.11 Startup and Shutdown Sequencing
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Filtered AC Coupled Single-Ended PWM Input Application
      3. 9.2.3 DC-Coupled DAC Input Application
      4. 9.2.4 DC-Coupled Reference Input Application
      5. 9.2.5 Flyback Circuit
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Boost + Amplifier Configuration Layout Considerations
      2. 11.1.2 Flyback Configuration Layout Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DRV2700 is intended to drive piezo loads. This includes: capacitive loads, piezo sounders, piezo valves, piezo positioning actuators, piezo micropumps, piezo polymers and more.

9.2 Typical Applications

9.2.1 AC-Coupled DAC Input Application

The AC-coupled DAC input circuit shown in Figure 22 is typically used in piezo speaker applications. AC-coupling the DRV2700 device allows the device to only amplify the differential portions of the input which minimizes the common-mode amplification. Because a digitized AC signal is provided from an external source, such as a microcontroller, an input filter is not required. However, a low-pass filter can be added to minimize the harmonics of the digitized waveform.

DRV2700 acCoupled_app_slos861.gifFigure 22. AC-Coupled DAC Input

9.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE CONSTRAINT
Input voltage 5 V Power source
Output voltage ±60 V Piezo load
Maximum output frequency 2 kHz Application

9.2.1.2 Detailed Design Procedure

To design the entire system follow the design procedure listed in the following sections.

9.2.1.2.1 Piezo Load Selection

Several key specifications must be considered when selecting a piezo actuator such as dimensions, blocking force, and displacement. However, the key electrical specifications from the driver perspective are voltage rating and capacitance. The DRV2700 device operating in boost + amplifier mode can drive a variety of capacitances, frequencies, and voltages. However to extend the range in one specification can decrease the range of another specification. For example, if driving audio tones around 1 kHz, a lower capacitance piezo or lower driving voltage may be required. Figure 23 shows a general guide to selecting the proper parameters.

DRV2700 D007_slos861.gifFigure 23. Maximum Frequency versus Maximum Voltage for Different Load Capacitances

Based on the design example, if the output voltage must be ±60 VOUT to 2 kHz, then the piezo capacitance must be less than 100 nF. For ease of calculation, use a piezo load capacitance of 25 nF.

9.2.1.2.2 Programming The Boost Voltage

The boost or flyback output voltage is programmed by an external network as shown in Figure 24.

DRV2700 boostCalDia_slos861.gifFigure 24. External Network

Depending on which configuration or mode is used in the system, use Equation 1 to calculate the output voltage.

Equation 1. DRV2700 boostFormula_slos861.gif

where

  • VFB = 1.30 V
  • VOP = VOL of the operational amplifier (op amp). Typically this can be approximated to 0 V.

The BST pin should be programmed to a value 5-V greater than the largest peak voltage in the system expected to allow adequate amplifier headroom. Because the programming range for the boost voltage extends to 105 V, the leakage current through the resistor divider becomes significant. TI recommends that the sum of the resistance of R(FB1) and R(FB2) be greater than 500 kΩ.

The flyback mode configuration may require filtering capacitors to go along with the feedback network to increase the performance at low and high frequencies. Because the charge storage is inversely proportional to the capacitance, use Equation 2 to calculate the values of the capacitors. In general, select a value of 22 pF for C(FB1).

For this design example, because the value of VPP must be negative, the boost + amplifier configuration must be used. Additionally, because the value of VBST must be 5 V more than VP, VBST is set to 65 V. Using Equation 1, the feedback resistors can be found such that RFB1 = 49 × RFB2. Because the total resistance must be greater than 500 kΩ, RFB1= 735 kΩ and RFB2= 15 kΩ.

Equation 2. DRV2700 Rfb_vs_Cfb_equ_slos861.gif

NOTE

When resistor values greater than 1 MΩ are used, PCB contamination causes boost voltage inaccuracy. Use caution when soldering large resistences, and clean the area when finished for best results.

9.2.1.2.3 Inductor and Transformer Selection

Inductor selection plays a critical role in the performance of the DRV2700 device. The range of recommended inductances is from 3.3 to 22 µH. In general, higher inductances within a given manufacturer’s inductor series have lower saturation current-limits and lower inductances have higher saturation current-limits. When a larger inductance is selected, the DRV2700 boost converter automatically runs at a lower switching frequency and incurs less switching losses. However, larger values of inductance may have higher ESR which increases the parasitic inductor losses. Because lower values of inductance generally have higher saturation currents, inductors with a lower value are a better choice when attempting to maximize the output current of the boost converter.

Another factor to consider for transformers is the winding ratio. In general, if a 200-V output is desired then, because the SW node can boost up to 100 V, a transformer of 1:2 (100 V:200 V) is the minimum required winding. However, selecting a slightly higher winding ratio to ensure that the 100 V on the primary side is not surpassed while trying to boost up to the desired voltage is good design practice.

For this design example, select an inductor of 3.3 µH with a saturation current of 1.5 A.

9.2.1.2.4 Programing the Boost and Flyback Current-Limit

The peak current drawn from the supply through the inductor is set solely by the R(REXT) resistor. This peak current-limit is independent of the selected inductance value, but the inductor is capable of handling this programmed limit. Use Equation 3 to calculate the relationship between R(REXT) and I(LIM).

Equation 3. DRV2700 EQ2_Rext_slos861.gif

where

  • K = 10 500
  • Vref = 1.35 V
  • I(LIM) is the desired peak current-limit through the inductor or transformer
  • R(INT) = 60 Ω

For this design example, because the saturation current is 1.5 A, select 1 A for the I(LIM) value. Using Equation 3, the value of R(EXT) is approximately 14 kΩ.

9.2.1.2.5 Boost Capacitor Selection

The boost output voltage is programmable as high as 105 V. A capacitor with a voltage rating of at least the boost output voltage must be selected. Because ceramic capacitors come in ratings of 100 V or 250 V, a 250-V rated 100-nF capacitor of the X5R or X7R type is recommended for the 105-V case. The selected capacitor should have a minimum working capacitance of at least 50 nF. If a smaller ripple on this node is required, then a larger capacitor should be selected. If using a differential output in the boost + amplifier configuration, then the ripple is canceled because it is prevelant on both the OUT+ and OUT– pins.

For this design example, a 100-nF capacitor was used.

9.2.1.2.6 Pulldown FET and Resistors

The pulldown FET and resistor are used to help speed up the drain the charge on the high-voltage output. Because the FET must be driven from a comparator, an NMOS FET must be used. During normal operation, the VDS of the NMOS is subject to a any value from approximately 0 V when the FET is on, to the output on the flyback configuration (V(HV)) when the FET is off. Therefore, selecting a FET with a VDS breakdown higher than the maximum VHV is required. Additionally, placing a resistor in series with this FET (on the drain side) to limit the current going through the FET is required. This resistor can be sized according to the maximum current allowed per the data sheet of the FET. As an additional measure, a resistor can be placed on the source side to protect the pulldown FET, such that when current flows through the resistor, it raises the source voltage and thereby lowers the VGS and shuts the FET off.

Because this design example is using the boost + amplifier configuration, the pulldown FET and resistors are not required.

9.2.1.2.7 Low-Voltage Operation

The lowest gain setting is optimized for 50 VPP with a boost voltage of 30 V. Some applications may not require 50 VPP, therefore the designer may choose to program the boost converter as low as 15 V to improve efficiency. When using boost voltages lower than 30 V, consider using a boost capacitor and adjusting the full-scale input range First, to reduce boost ripple to an acceptable level, a 50-V rated, 0.22-µF boost capacitor is recommended. Second, the full-scale input range may require adjustment to avoid clipping. Generally, a 1.8-V single-ended PWM signal provides 50 VPP at the lowest gain. For example, if the boost voltage is set to 25 V for a 40 VPP full-scale output signal, the full-scale input range drops to 1.44 V for single-ended PWM inputs. An input voltage divider may be desired in this case if a 1.8-V I/O is used as a PWM source.

9.2.1.2.8 Current Consumption Calculation

Understanding how the voltage driven onto a piezo actuator relates to the current consumption from the power supply is useful. Modeling a piezo element as a pure capacitor is reasonably accurate. Use Equation 4 to calculate the current through a capacitor for an applied sinusoid.

Equation 4. DRV2700 EQ_Icap_slos861.gif

where

  • ƒ is the frequency of the sinusoid in hertz
  • C is the capacitance of the piezo load in farads
  • VP is the peak voltage

At the power supply, the actuator current is multiplied by the boost-supply ratio and divided by the efficiency of the boost converter as shown in Equation 5.

Equation 5. DRV2700 EQ_Ibat1_slos861.gif

Substituting the design example values for the variables into Equation 5 and using a boost efficiency of 60%, yields a typical peak current from the power supply of 408 mA as shown in Equation 6.

Equation 6. DRV2700 EQ_Ibat1_values_slos861.gif

9.2.1.2.9 Input Filter Considerations

Depending on the quality of the source signal provided to the DRV2700 device, an input filter may be required. Some key factors to consider are whether the source is generated from a DAC or from PWM, and the out-of-band content generated. If proper anti-image rejection filtering is used to eliminate image components, the filter can possibly be eliminated depending on the magnitude of the out-of-band components. If PWM is used, at least a first-order RC filter is required. The PWM sample rate must be greater than 30 kHz to keep the PWM ripple from reaching the piezo element and dissipating unnecessary power. A second-order RC filter may be desirable to further eliminate out-of-band signal content to further drive down power dissipation and eliminate audible noise.

For this design example, to ensure higher harmonics of the input signal do not propagate into the device, use a low pass filter with a 3-dB point of 2 kHz. Refer to DRV2700EVM High Voltage Piezo Driver Evaluation Kit, SLOU403, to build this input filter network.

9.2.1.2.10 Output Limiting Factors

Because of the small size of the DRV2700 device, limiting factors must be considered. In each of the applications, four factors can affect the output. These factors include the following:

  • Bandwidth of the amplifier
  • Limited current
  • Slew rate
  • Thermal shutdown

Although some of these factors can appear at the same time, each of these factors are shown in the following figures to help the designer differentiate between each factor.

DRV2700 D005_slos861.gifFigure 25. Bandwidth and Limited Current

The internal amplifier has an inherent bandwidth limitation on the order of 5 to 20 kHz depending on the gain settings. Although, this bandwidth limitation occurs primarily with a no-load condition or under a very small voltage swing, the output is essentially unable to drive to the expected output voltage because of a drop in the gain at that bandwidth. The internal boost converter can only support a limited amount of current. If for instance, the load was somewhat resistive as opposed to only capacitive, a situation could occur where the load requires additional current to pull the voltage up, however the boost converter cannot support it. This situation appears to be an out-of-regulation output voltage.

DRV2700 D006_slos861.gifFigure 26. Slew Rate and Thermal Shutdown

As the output frequency increases, the slew rate increases. Because the boost converter can only support a certain amount of current based on the load capacitance, the sine wave begins to turn into more of a triangle wave.

Lastly, the device has a thermal shutdown feature for protection from damaging when the device begins to heat up because of power dissipation. When a load is primarily capacitance, the current leads the voltage (leading power factor). With a leading or lagging power factor, the maximum power does not occur at the maximum voltage or current. However the maximum power does occur at the phase crossing of these. This occurrence looks similar to the waveform in Figure 26, such that the output goes to 0 V and then start back up after it has cooled down below the internal threshold. Figure 23 shows a general guideline to staying below the maximum voltage and frequency based on the capacitance of the load.

9.2.1.2.11 Startup and Shutdown Sequencing

A simple startup sequence is employed to maintain smooth operation. If the sequence is not followed, unintended events my occur.

Use the following steps to startup the device in boost + amplifier mode:

  1. Transition the DRV2700 enable pin from logic-low to logic-high.
  2. Wait 2 ms to ensure that the DRV2700 circuitry is fully enabled and settled.
  3. Provide a PWM, audio, or DAC source to be amplified through the DRV2700 device. When the input waveform is complete, continue to step 4.
  4. Transition the DRV2700 enable pin from high to low.

Use the following steps to startup the device in flyback mode:

  1. Set the processor output to 0 V to set the feedback network to such that VHV = 0 V. This setting ensures that VHV does not spike when the device is enabled.
  2. Transition the DRV2700 enable pin from logic-low to logic-high.
  3. Wait 2 ms to ensure that the DRV2700 circuitry is fully enabled and settled.
  4. Begin and complete playback of the waveform from the processor. When the input waveform is complete, continue to step 4.
  5. Transition the DRV2700 enable pin from high to low and power down the DAC source.

9.2.1.3 Application Curves

DRV2700 accoupled_gain_40.7_slos861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 105 V
G = 40.7 dB
Figure 27. AC Coupled Differential Output
DRV2700 DCcoupled_set_reference_slos861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 105 V
G = 28.8 dB
Figure 29. DC Coupled Differential Output
DRV2700 C22nF_woPulldown_slos861.gif
VDD = 5 V C(LOAD) = 22 nF VHV = 0 to 500 V
Figure 31. High Voltage Mode without FET Pulldown
DRV2700 accoupled_gain_28.8_slos861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 105 V
G = 28.8 dB
Figure 28. AC Coupled Differential Output
DRV2700 C22nF_withPulldown_slos861.gif
VDD = 5 V C(LOAD) = 22 nF VHV = 0 to 500 V
Figure 30. High Voltage Mode with FET Pulldown
DRV2700 ArbWaveWithPulldown_slos861.gif
VDD = 5 V C(LOAD) = 22 nF VHV = 0 to 500 V
Figure 32. High Voltage Mode Arbitrary Waveform

9.2.2 Filtered AC Coupled Single-Ended PWM Input Application

The AC coupled single-ended PWM input is very similar to the application described in the AC-Coupled DAC Input Application section, however because the input is a true PWM signal, a low-pass filter is highly recommended. Typically, a low cutoff frequency is desired to ensure the higher frequencies have been attenuated and are not amplified.

DRV2700 acCoupledPWM_app_slos861.gifFigure 33. Filtered AC Coupled Single-Ended PWM Input

9.2.3 DC-Coupled DAC Input Application

The DC-coupled DAC input is used in applications when the user might need to drive the output at a constant DC level. A typical application for th the DC-coupled DAC input is for piezo pneumatic valves. A benefit to this application circuit is that all of the inputs, including power, are at a very low voltage while keeping the high-voltage piezo load separated. This feature allows easy implementation into systems and to help separate or isolate the high voltages loads from the critical controls.

Piezoelectric materials have a certain voltage that debias the piezo phenomenon. To prevent this debiasing from occurring, limit the input using a controlled input signal. As a backup measure, place a Zener diode to restrict the input.

DRV2700 dcCoupledPWM_app_slos861.gifFigure 34. DC-Coupled DAC Input

9.2.4 DC-Coupled Reference Input Application

The DC-coupled referenced to VDD input is used in applications when the user might need to drive the output at a constant DC level in an on-off implementation. A typical application for this configuration is for piezo pneumatic valves. A benefit to this application circuit is that all of the inputs, including power, are at a very low voltage while keeping the high-voltage piezo load separated. Additionally, all that is required is the VDD input. This feature allows easy implementation into systems and to help separate or isolate the high voltages loads from the critical controls.

As mentioned in the previous section, piezoelectric materials have a certain voltage that debias the piezo phenomenon. This configuration protects the piezo from negative voltages because the input is always positive.

DRV2700 dcCoupledSimpleWithAmp_app_slos861.gifFigure 35. DC-Coupled Referenced Input

This application circuit can also be altered to only use the boost as shown in Figure 36. The benefits of altering this circuit is that it requires less components and has better power efficiency because no power is used in the amplifier. The drawback is that ripple occurs on the piezo element and the fall time of the output is longer because it is drained based on the RC time constant on the BST node.

DRV2700 dcCoupledSimpleNoAmp_app_slos861.gifFigure 36. Boost Driving Piezo

9.2.5 Flyback Circuit

The flyback circuit is intended for applications using piezo valves, piezo polymers, and other high-voltage loads. The previously listed applications go from ±100 V, however this circuit can go up to even higher voltages (1 kV for example) depending on the feedback network and maximum operating conditions of the external components. The input is controlled using PWM, a DAC, or a purely analog signal. Therefore, a proper input filter may be required as discussed in the previous application circuits.

The increased voltage range, however, comes at a price. As the output voltage increases, the capable output sourcing current is lowered. However, because most piezo loads require a small current for the holding or blocking force, the drop in current may not impact the performance of the application. Figure 37 shows a typical flyback circuit.

DRV2700 flyback_app_slos861.gifFigure 37. Flyback Circuit

The following sections shown in Figure 37 must be explained:

  • Op-amp integrator
  • Comparator and pulldown FET
  • C(HV) value

The op-amp integrator shown at the bottom of the circuit in Figure 37, is used to control the output voltage. Because the input can be a PWM or DAC signal, it helps smooth out the input signal. Additionally, the output controls the virtual ground of the feedback network. For example, when the output of the integrator is equal to VOL (approximately 0 V), the current through R(FB2) is at the maximum and therefore increase the current (and voltage) on R(FB1) which raises the voltage across the piezo load. Likewise, as the output voltage of the integrator increases, it then decreases the current through R(FB2) and therefore decreases the voltage on R(FB1), which lowers the voltage across the piezo load.

The comparator and pulldown FET are used to drain the charge on the high-voltage output. Because a high resistance (or low current) is desired through for the feedback network, the RC-time constant of draining charge can be very long. To help with this long RC-time constraint, the comparator and pulldown FET are added to drain charge when VFB > Vref which adds a low resistance in parallel and therefore lowers the RC time constant. Ensure that this pulldown network can support the voltage and the current. As shown in Figure 30 and Figure 31, the pulldown allows for better regulation and faster stopping time.

Lastly, the C(HV) value is determined by the system. A value of >1-nF total capacitance is required on the high-voltage node for proper regulation. This total capacitance is the combination of the piezo load and the onboard C(HV).

NOTE

As the capacitance increases, the voltage ripple on the output decreases. However, this decrease in ripple also slows down the startup or slew rate on the output. Ensure that the C(HV) and the piezo load can support the high voltage across C(HV) and the load.

9.3 System Example

To use the DRV2700 in a system, all that is required is a controller for the input signal and digital control, power management to provide power to the device, and a high-voltage load. Figure 38 shows a typical system diagram using the DRV2700 device. Because most systems already include some type of controller and power management, the DRV2700 device can easily be added to an existing system.

DRV2700 typicalSystem_sch_slos861.gifFigure 38. DRV2700 System Diagram