SLOS861B March   2015  – April 2015 DRV2700

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Boost + Amplifier Configuration
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Boost Converter and Control Loop
      2. 8.3.2 High-Voltage Amplifier
      3. 8.3.3 Fast Start-Up (Enable Pin)
      4. 8.3.4 Gain Control
      5. 8.3.5 Adjustable Boost Voltage
      6. 8.3.6 Adjustable Boost Current-Limit
      7. 8.3.7 Internal Charge Pump
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Boost + Amplifier Mode
      2. 8.4.2 Flyback Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 AC-Coupled DAC Input Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Piezo Load Selection
          2. 9.2.1.2.2  Programming The Boost Voltage
          3. 9.2.1.2.3  Inductor and Transformer Selection
          4. 9.2.1.2.4  Programing the Boost and Flyback Current-Limit
          5. 9.2.1.2.5  Boost Capacitor Selection
          6. 9.2.1.2.6  Pulldown FET and Resistors
          7. 9.2.1.2.7  Low-Voltage Operation
          8. 9.2.1.2.8  Current Consumption Calculation
          9. 9.2.1.2.9  Input Filter Considerations
          10. 9.2.1.2.10 Output Limiting Factors
          11. 9.2.1.2.11 Startup and Shutdown Sequencing
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Filtered AC Coupled Single-Ended PWM Input Application
      3. 9.2.3 DC-Coupled DAC Input Application
      4. 9.2.4 DC-Coupled Reference Input Application
      5. 9.2.5 Flyback Circuit
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Boost + Amplifier Configuration Layout Considerations
      2. 11.1.2 Flyback Configuration Layout Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage VDD –0.3 6 V
Input voltage IN+, IN–, EN, GAIN0, GAIN1, FB –0.3 VDD + 0.3 V
Boost/Output Voltage PVDD, SW, OUT+, OUT– 120 V
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 °C
Operating free-air temperature, TA –40 85 °C
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins ±2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins ±1500

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage VDD 3 5.5 V
V(BST) Boost voltage BST 15 105 V
VID Differential input voltage IN+, IN– 1.8(1) V
VIL Digital input low voltage EN, GAIN0, GAIN1; VDD = 3.6 V 0.75 V
VIH Digital input high voltage EN, GAIN0, GAIN1; VDD = 3.6 V 1.4 V
R(REXT) Current-limit control resistor 6 35
L Inductance for boost converter 3.3 µH
(1) Gains are optimized for a 1.8-V peak input

7.4 Thermal Information

THERMAL METRIC(1) RGP (VQFN)
20 PINS
UNIT
RθJA Junction-to-ambient thermal resistance 33.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 30.9
RθJB Junction-to-board thermal resistance 8.7
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 8.7
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C, VOUT(PP) = VOUT+ – VOUT– = 200 V, C(LOAD) = 47 nF, G(AMP) = 40 dB, L = 4.7 µH (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|IIL| Digital-input low current EN, GAIN0, GAIN1; VDD = 3.6 V, VI = 0 V 1 µA
|IIH| Digital-input high current EN, GAIN0, GAIN1; VDD = 3.6 V, VI = VDD 5 µA
IL(sd) Shutdown current VDD = 3.6 V, V(EN) = 0 V 13 µA
IQ Quiescent current VDD = 3.6 V, V(EN) = VDD, V(BST) = 105 V, no signal 24 mA
VDD = 3.6 V, V(EN) = VDD, V(BST) = 80 V, no signal 13 mA
VDD = 3.6 V, V(EN) = VDD, V(BST) = 55 V, no signal 9 mA
VDD = 3.6 V, V(EN) = VDD, V(BST) = 30 V, no signal 5 mA
VOS Offset voltage VDD = 3.6 V, V(EN) = 3.6 V 25 mV
CMVR Common-mode voltage VDD = 3.6 V, V(EN) = 3.6 V 0.2 VDD – 0.4 V
CMRR Common-mode rejection ratio VDD = 3.6 V, V(EN) = 3.6 V 100 dB
PSRR Power-supply rejection ratio VDD = 3.6 V, V(EN) = 3.6 V 60 dB
RI Input impedance All gains, IN+, IN– 100
G(AMP) Amplifier gain GAIN[1:0] = 00 28.8 dB
GAIN[1:0] = 01 34.8
GAIN[1:0] = 10 38.4
GAIN[1:0] = 11 40.7
SR Slew rate GAIN[1:0] = 00, No Load 150 V/ms
GAIN[1:0] = 01, No Load 300
GAIN[1:0] = 10, No Load 450
GAIN[1:0] = 11, No Load 600
BW Amplifier bandwidth GAIN[1:0] = 00, VOUT(PP) = 50 V, No Load 20 kHz
GAIN[1:0] = 01, VOUT(PP) = 100 V, No Load 10
GAIN[1:0] = 10, VOUT(PP) = 150 V, No Load 7.5
GAIN[1:0] = 11, VOUT(PP) = 200 V, No Load 5
GBW Gain-bandwidth product VDD = 3.6 V, V(EN) = 3.6 V 550 kHz
Vn Input Voltage Noise VDD = 3.6 V, V(EN) = 3.6 V 6.5 µV/√Hz
THD+N Total harmonic distortion plus noise ƒ = 300 Hz, VOUT(PP) = 200 V 1%

7.6 Switching Characteristics

VDD = 3.6 V, TA = 25°C, VOUT(PP) = VOUT+ – VOUT– = 200 V, C(LOAD) = 47 nF, G(AMP) = 40 dB, L = 4.7 µH (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(start) Startup time—time from EN high until boost and amplifier are fully enabled 1.5 ms
ƒMIN Minimum startup switching frequency 39 kHz

7.7 Typical characteristics

VDD = 3.6 V, R(REXT) = 7.5 kΩ, L = 4.7 µH, differential input, 100-nF DC blocking capacitors on IN±
DRV2700 D001_slos861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 30 V
G = 28.8 dB
Figure 1. Load Current vs Boost Efficiency (%) and Voltage (V) at VPVDD = 30 V
DRV2700 D003_slos861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 80 V
G = 38.4 dB
Figure 3. Load Current vs Boost Efficiency (%) and Voltage (V) at VPVDD = 80 V
DRV2700 Fig5_VBST_Line_Regulation_VBST_105V_SLOS861.gif
G = 40.7 dB C(LOAD) = Open VPVDD = 105 V
Figure 5. Line Regulation at PVDD = 105 V
DRV2700 Fig7_Amp_AC_PSRR_VBST_105V_SLOS861.gif
G = 40.7 dB C(LOAD) = Open VPVDD = 105 V
Figure 7. AC PSRR at VPVDD = 105 V
DRV2700 Fig9_Amp_Gain_Bandwidth_VBST_30V_SLOS861.gif
VDD = 3.6 V G = 28.8 dB VPVDD = 30 V
Figure 9. Gain Bandwidth at VPVDD = 30 V
DRV2700 Fig11_Amp_Gain_Bandwidth_VBST_80V_SLOS861.gif
VDD = 3.6 V G = 38.4 dB VPVDD = 80 V
Figure 11. Gain Bandwidth at VPVDD = 80 V
DRV2700 Fig13_Amp_Output_Linearity_Gain(11)_SLOS861.gif
VDD = 3.6 V G = 40.7 dB C(LOAD) = Open
Figure 13. Output Linearity
DRV2700 Fig14_Amp_Slew_Rate_VBST_105V_SLOS861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 105 V
G = 40.7 dB
Figure 15. Output Slew Rate
DRV2700 Fig7_THDN_vs_Vo_1_slos861_slos861.gif
ƒ = 200 Hz C(LOAD) = 47 nF VPVDD = 105 V
G = 40 dB
Figure 17. Total Harmonic Distortion + Noise vs Output Voltage
DRV2700 Fig11_THDN_vs_Vo_3_slos861.gif
ƒ = 200 Hz C(LOAD) = 680 nF VPVDD = 30 V
G = 28 dB
Figure 19. Total Harmonic Distortion + Noise vs Output Voltage
DRV2700 Fig15_Feedback_Voltage_vs_Temp_VBST_105V_SLOS861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 105 V
G = 40.7 dB
Figure 21. R(REXT) Voltage vs Temperature
DRV2700 D002_slos861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 55 V
G = 34.8 dB
Figure 2. Load Current vs Boost Efficiency (%) and Voltage (V) at VPVDD = 55 V
DRV2700 D004_slos861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 105 V
G = 40.7 dB
Figure 4. Load Current vs Boost Efficiency (%) and Voltage (V) at VPVDD = 105 V
DRV2700 Fig6_VBST_Startup_VBST_105V_SLOS861.gif
VDD = 3.6 V C(LOAD) = Open VPVDD = 105 V
G = 40.7 dB
Figure 6. Boost Voltage Startup
DRV2700 Fig8_Amp_AC_CMRR_VBST_105V_SLOS861.gif
G = 40.7 dB C(LOAD) = Open VPVDD = 105 V
Figure 8. AC CMRR at VPVDD = 105 V
DRV2700 Fig10_Amp_Gain_Bandwidth_VBST_55V_SLOS861.gif
VDD = 3.6 V G = 34.8 dB VPVDD = 55 V
Figure 10. Gain Bandwidth at VPVDD = 55 V
DRV2700 Fig12_Amp_Gain_Bandwidth_VBST_105V_SLOS861.gif
VDD = 3.6 V G = 40.7 dB VPVDD = 105 V
Figure 12. Gain Bandwidth at VPVDD = 105 V
DRV2700 Fig13_Amp_Output_Linearity_Gain(11_10_01_00)_SLOS861.gif
VDD = 3.6 V C(LOAD) = Open
G = 28.8 dB at VPVDD = 30 V G = 34.8 dB at VPVDD = 55 V
G = 38.4 dB at VPVDD = 80 V G = 40.7 dB at VPVDD = 105 V
Figure 14. Output Linearity with Different Gains
DRV2700 Fig1_Supply_Current_vs_Output_Voltage_200Hz_Gain_40dB_47nF_slos861.gif
ƒ = 200 Hz C(LOAD) = 47 nF VPVDD = 105 V
G = 40 dB
Figure 16. Supply Current vs Output Voltage
DRV2700 Fig9_THDN_vs_Vo_2_slos861_slos861.gif
ƒ = 200 Hz C(LOAD) = 330 nF VPVDD = 55 V
G = 34 dB
Figure 18. Total Harmonic Distortion + Noise vs Output Voltage
DRV2700 Fig12_Theoret_REXT_slos861.gif
Figure 20. Inductor Current vs R(REXT)