SLASF54 January   2023 DRV2901

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Block Diagrams
    2. 7.2 Feature Description
      1. 7.2.1 Error Reporting
      2. 7.2.2 Device Reset
      3. 7.2.3 Device Protection System
        1. 7.2.3.1 Overcurrent (OC) Protection With Current Limiting and Overload Detection
        2. 7.2.3.2 Overtemperature Protection
        3. 7.2.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Power Supply Recommendations
    1. 9.1 System Power-up/power-down Sequence
      1. 9.1.1 Powering Up
      2. 9.1.2 Powering Down
    2. 9.2 System Design Recommendations
      1. 9.2.1 VDD Pin
      2. 9.2.2 VREG Pin
      3. 9.2.3 OTW Pin
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 DDV Package44-Pin HTSSOP PowerPadTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 11 P Analog ground
BST_A 34 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_A required
BST_B 33 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_B required
GND 6, 10, 14, 18, 28, 29, 38, 39 P Ground.
GND_A 37 P Power ground for half-bridge A
GND_B 30 P Power ground for half-bridge B
GVDD_A 1, 44 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND
GVDD_B 22, 23 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND
NC 3, 4, 19, 20, 24, 25, 26, 27, 40, 41, 42, 43 — Do not connect.
OC_ADJ 9 O Analog overcurrent programming pin requires resistor to ground
OTW 2 O Overtemperature warning signal, open-drain, active-low
OUT_A 36 O Output, half-bridge A
OUT_B 31 O Output, half-bridge B
PVDD_A 35 P Power supply input for half-bridge A requires close decoupling of 0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_A.
PVDD_B 32 P Power supply input for half-bridge B requires close decoupling of 0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_B.
PWM_A 8 I Input signal for half-bridge A
PWM_B 16 I Input signal for half-bridge B
RESET 7, 17 I Reset signal for half-bridge A and B, active-low
SD 5 O Shutdown signal, open-drain, active-low
VDD 21 P Power supply for digital voltage regulator requires a 47-μF capacitor in parallel with a 0.1-μF capacitor to GND for decoupling.
VREG 12, 13, 15 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
(1) I = input, O = output, P = power