SBAS640A January   2018  – June 2020 DRV5055

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Schematic
      2.      Magnetic Response
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Magnetic Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Magnetic Flux Direction
      2. 7.3.2 Magnetic Response
      3. 7.3.3 Sensitivity Linearity
      4. 7.3.4 Ratiometric Architecture
      5. 7.3.5 Operating VCC Ranges
      6. 7.3.6 Sensitivity Temperature Compensation for Magnets
      7. 7.3.7 Power-On Time
      8. 7.3.8 Hall Element Location
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selecting the Sensitivity Option
      2. 8.1.2 Temperature Compensation for Magnets
      3. 8.1.3 Adding a Low-Pass Filter
      4. 8.1.4 Designing for Wire Break Detection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Designing for Wire Break Detection

Some systems must detect if interconnect wires become open or shorted. The DRV5055 can support this function.

First, select a sensitivity option that causes the output voltage to stay within the VL range during normal operation. Second, add a pullup resistor between OUT and VCC. TI recommends a value between 20 kΩ to 100 kΩ, and the current through OUT must not exceed the IO specification, including current going into an external ADC. Then, if the output voltage is ever measured to be within 150 mV of VCC or GND, a fault condition exists. Figure 19 shows the circuit, and Table 1 describes fault scenarios.

DRV5055 wire2.gifFigure 19. Wire Fault Detection Circuit

Table 1. Fault Scenarios and the Resulting VOUT

FAULT SCENARIO VOUT
VCC disconnects Close to GND
GND disconnects Close to VCC
VCC shorts to OUT Close to VCC
GND shorts to OUT Close to GND