SLVSJF0 October   2025 DRV7167

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information_DRV7167A
    5. 5.5 Electrical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Bootstrap Supply Regulation
      4. 7.3.4 Level Shift
      5. 7.3.5 Zero Voltage Detection (ZVD) Reporting
      6. 7.3.6 Short Circuit Protection (SCP)
      7. 7.3.7 Over Temperature Detection (OTD)
      8. 7.3.8 Fault Indication
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application - PWM Mode
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information
      1. 11.1.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Zero Voltage Detection (ZVD) Reporting

The DRV7167A supports Zero-Voltage Detection (ZVD) to indicate whether the high-side and low-side FETs transitioned to third-qadrant in any transition. This information is reported on ZVDH (for high-side FET) and ZVDL (for low-side FET) pins. This feature is only available in the IIM mode.

For the low-side FET if in a particular transition the switch node falls VTHRESH_ZVD below AGND for a time period greater than t3RD_ZVD, a low pulse of tWD_ZVD is generated with a delay of tDLY_ZVD_L.

For the high-side FET if in a particular transition the switch node rises VTHRESH_ZVD above VM for a time period greater than t3RD_ZVD, a low pulse of tWD_ZVD is generated after a one PWM cycle, with a delay of tDLY_ZVD_H from the corresponding LI transition.

A controller using DRV7167A can use the ZVD information to adjust dead-times and minimze the third quadrant conduction time of the high-side and low-side FETs.