SLVSJF0 October   2025 DRV7167

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information_DRV7167A
    5. 5.5 Electrical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Mismatch Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Inputs
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 Bootstrap Supply Regulation
      4. 7.3.4 Level Shift
      5. 7.3.5 Zero Voltage Detection (ZVD) Reporting
      6. 7.3.6 Short Circuit Protection (SCP)
      7. 7.3.7 Over Temperature Detection (OTD)
      8. 7.3.8 Fault Indication
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application - PWM Mode
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Information
      1. 11.1.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Unless otherwise noted, voltages are with respect to AGND and typical specifications are at 25℃ (1); -40℃ ≤ TJ ≤150℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER STAGE_DRV7167A
RDS(ON)HS High-side GaN FET on-resistance LI=0V, HI=GVDD=5V, BOOT-HS=5V, I(VM-OUT)=16A, TJ = 25℃ 2.3 3.1 mΩ
RDS(ON)LS Low-side GaN FET on-resistance LI=GVDD=5V, HI=0V, BOOT-HS=5V, I(OUT-PGND)=16A, TJ = 25℃ 2.2 3 mΩ
VSD GaN source to drain 3rd quadrant conduction drop ISD = 500 mA, VM floating, VGVDD = 5 V, HI = LI = 0V 1.5 V
IL-VM-OUT Leakage from VM to OUT when the high-side GaN FET and low-side GaN FET are off VM = 80V, OUT=0V, HI = LI = 0V, VGVDD = 5V, TJ=25℃ 10 150 µA
IL-VM-OUT Leakage from VM to OUT when the high-side GaN FET and low-side GaN FET are off VM = 80V, OUT=0V, HI = LI = 0V, VGVDD = 5V, TJ=90℃ 20 300 µA
IL-OUT-GND Leakage from OUT to GND when the high-side GaN FET and low-side GaN FET are off OUT = 80V, HI = LI = 0V, VGVDD = 5V, TJ=25℃ 10 150 µA
IL-OUT-GND Leakage from OUT to GND when the high-side GaN FET and low-side GaN FET are off OUT = 80V, HI = LI = 0V, VGVDD = 5V, TJ=90℃ 20 300 µA
CISS Input Capacitance of high side or low side HEMT VDS=50V, VGS= 0V (HI = LI = 0V), TJ=25℃ 1700 pF
COSS Output Capacitance of high-side GaN FET or low-side GaN FET VDS=50V, VGS= 0V (HI = LI = 0V), TJ=25℃ 570 pF
COSS(ER) Output Capacitance of high-side GaN FET or low-side GaN FET - Energy Related VDS=0 to 50V, VGS= 0V (HI = LI = 0V), TJ=25℃ 700 pF
COSS(TR) Output Capacitance of high-side GaN FET or low-side GaN FET - Time Related VDS=0 to 50V, VGS= 0V (HI = LI = 0V), TJ=25℃ 880 pF
CRSS Reverse Transfer Capacitance of high side or low side HEMT VDS=50V, VGS= 0V (HI = LI = 0V), TJ=25℃ 4.3 pF
QG Total Gate Charge of high side or low side HEMT VDS=50V, ID= 16A, VGS= 5V, TJ=25℃ 12 nC
QGD Gate to Drain Charge of high side or low side HEMT VDS=50V, ID= 16A, TJ=25℃ 1.2 nC
QGS Gate to Source Charge of high side or low side HEMT VDS=50V, ID= 16A, TJ=25℃ 3.9 nC
QOSS Output Charge (sum of high side HEMT, low side HEMT and gate-driver HV-Well charge)  VDS=50V, ID= 16A, TJ=25℃ 90 nC
QRR Source to Drain Reverse Recovery Charge 0 nC
tHIPLH Propagation delay: HI Rising(2) LI=0V, GVDD=5V, BOOT-HS=5V, VM=48V 15 25 ns
tHIPHL Propagation delay: HI Falling(2) LI=0V, GVDD=5V, BOOT-HS=5V, VM=48V 15 25 ns
tLIPLH Propagation delay: LI Rising(2) HI=0V, GVDD=5V, BOOT-HS=5V, VM=48V 15 25 ns
tLIPHL Propagation delay: LI Falling(2) HI=0V, GVDD=5V, BOOT-HS=5V, VM=48V 15 25 ns
tMON Delay Matching: LI high & HI low(2) 2 5 ns
tMOFF Delay Matching: LI low & HI high(2) 2 5 ns
tPW Minimum Input Pulse Width that Changes the Output 10 ns
INPUT PINS (ENIN/HI, PWM/LI, EN)
VIH High-Level Input Voltage Threshold Rising Edge 2.1 V
VIL Low-Level Input Voltage Threshold Falling Edge 1.2 V
VHYS Hysteresis between rising and falling threshold 300 mV
RI Input pull down resistance 200 300 500 kΩ
OUTPUT PINS (ZVDx)
VOL Low level output voltage IOL = 3 mA 0.25 V
VOH High level output voltage IOL = -1.5 mA to 0 mA 2.6 3.5 V
UNDER/OVER VOLTAGE PROTECTION
VGVDDR VGVDD Rising edge threshold Rising 3.3 3.6 3.9 V
VGVDDF VGVDD Falling edge threshold 3.1 3.4 3.7 V
VGVDD(hyst) VGVDD UVLO threshold hysteresis 200 mV
VBOOTR BOOT Rising edge threshold Rising 3.3 3.6 3.9 V
VBOOTF BOOT Falling edge threshold 3.1 3.4 3.7 V
VBOOT(hyst) BOOT UVLO threshold hysteresis 200 mV
VBOOTth BOOT Regulation Voltage thresholds 4.5 5.3 V
tPWRUP Power Up time after Digital Reset  50 µs
SYNCRONOUS BOOTSTRAP 
VDH Forward voltage drop IVDD-BOOT = 5mA 40 mV
IVDD-BOOT = 50mA 400 mV
tSS BOOT power up time (With LI=High) CBOOT = 220 nF 2.2 µs
tSS BOOT power up time (With LI=High) CBOOT = 1 µF 10 µs
SUPPLY CURRENTS
IGVDD GVDD Quiescent Current LI = HI = 0V, GVDD = 5V,  EN=0 0.3 mA
IGVDD GVDD Quiescent Current LI = HI = 0V, GVDD = 5V 0.9 3.5 mA
IGVDD GVDD Quiescent Current LI=GVDD=5V, HI=0V 1.8 7 mA
IGVDDO Total GVDD Operating Current f = 500 kHz, 50% Duty cycle, VM = 48V  12 15 mA
IBOOT BOOT Quiescent Current LI = HI = 0V, GVDD = 5V, BOOT-HS = 5V 0.5 1 mA
IBOOT BOOT Quiescent Current LI=0V, HI=GVDD=5V, BOOT-HS=5V, VM=48V 0.8 3.5 mA
IBOOTO BOOT Operating Current f = 500 kHz, 50% Duty cycle, GVDD = 5V, BOOT-HS = 5V, VM = 48V  5.6 8 mA
SLEW RATE CONTROL (EFFECTIVE GATE RESISTANCE)
Rgfh RDHF = 0 Ω Voltage across driver FET = 1.2V 0.3 Ω
RDHF = 4 kΩ 1.3
RDHF = 8 kΩ 2.6
RDHF =16 kΩ 5.3
Rgfl RDLF = 0 Ω Voltage across driver FET = 1.2V 0.3 Ω
RDLF = 4 kΩ 1.3
RDLF = 8 kΩ 2.6
RDLF =16 kΩ 5.3
Rgrh RDHR = 0 Ω Voltage across driver FET = 1.2V 0.8 Ω
RDHR = 4 kΩ 3.6
RDHR = 8 kΩ 7
RDHR =16 kΩ 14
Rgrl RDLR = 0 Ω Voltage across driver FET = 1.2V 0.8 Ω
RDLR = 4 kΩ 3.6
RDLR = 8 kΩ 7
RDLR =16 kΩ 14
DEAD TIME CONTROL
tDEAD_MIN Minimum Dead Time DLH, DHL = 0Ω; Minimum Dead time setting.   5 7.5  10 ns
tDEAD_MAX Maximum Dead Time DLH, DHL = 100kΩ; Maximum Dead time setting.   32 40 48 ns
OCP
VDSAT Saturation protection voltage threshold 0.75 V
tBLANK Blanking time for VDSAT detection 38 60 88 ns
tSATFLT Time to indicate FLT upon VDS overvoltage detection after blanking time 28.7 ns
ZVD Output (Active Low)
VTHRESH_ZVD ZVD Detector Threshold 0.8 1.0 V
t3RD_ZVD Minimum third quadrant time that can be detected by ZVD detector (Low Side) For a 0 to -1.5V to 0 pulse with 100ps rise/fall time 6 10 14 ns
t3RD_ZVD Minimum third quadrant time that can be detected by ZVD detector (High Side) For a 0 to -1.5V to 0 pulse with 100ps rise/fall time 6 10 14 ns
tDLY_ZVD_L Delay between VTHRESH_ZVD cross vs ZVD output going low
For a 0 to -1.5V to 0 pulse with 100ps rise/fall time
 		 20 30 ns
tDLY_ZVD_H Delay between VTHRESH_ZVD cross vs ZVD output going low
For a 0 to -1.5V to 0 pulse with 100ps rise/fall time
 		 20 30 ns
tWD_ZVD ZVD pulse width
For a 0 to -1.5V to 0 pulse with 100ps rise/fall time

 40 65 95 ns
OTD
OTD+ Over Temperature Detect high threshold 145 165 182 ℃
OTD- Over Temperature Detect high threshold 135 154 170
℃
OTDHYS Over Temperature Detect high threshold 12
℃
FAULT
IFLT Fault pin pull down current VFLT = 0.4 V 3 mA
tFLTDLY Time to indicate FLT after fault occurs 20 ns
tFLT Min fault indication time 10 µs
tENBLK Time after FLT release, after which EN=0 is effective 1 µs
(1) Parameters that show only a typical value are determined by design and may not be tested in production
(2) See Propagation Delay and Mismatch Measurement section