SLDS274A September   2024  – March 2025 DRV81242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active Mode
          5. 7.3.2.1.5 Limp Home Mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Reverse Current Behavior
        5. 7.3.3.5 Switching Channels in parallel
        6. 7.3.3.6 Bulb Inrush Mode (BIM)
        7. 7.3.3.7 Integrated PWM Generator
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home Mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
        9. 7.3.4.9 Open Load Detection in ON State
          1. 7.3.4.9.1 Open Load at ON - direct channel diagnosis
          2. 7.3.4.9.2 Open Load at ON - diagnosis loop
          3. 7.3.4.9.3 OLON bit
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Bulb Inrush Mode Register
          4. 7.3.5.4.4  Input 0 Mapping Register
          5. 7.3.5.4.5  Input 1 Mapping Register
          6. 7.3.5.4.6  Input Status Monitor Register
          7. 7.3.5.4.7  Open Load Current Control Register
          8. 7.3.5.4.8  Output Status Monitor Register
          9. 7.3.5.4.9  Open Load at ON Register
          10. 7.3.5.4.10 EN_OLON Register
          11. 7.3.5.4.11 Configuration Register
          12. 7.3.5.4.12 Output Clear Latch Register
          13. 7.3.5.4.13 FPWM Register
          14. 7.3.5.4.14 PWM0 Configuration Register
          15. 7.3.5.4.15 PWM1 Configuration Register
          16. 7.3.5.4.16 PWM_OUT Register
          17. 7.3.5.4.17 MAP_PWM Register
          18. 7.3.5.4.18 Configuration 2 Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Suggested External Components
      2. 8.1.2 Application Plots
    2. 8.2 Typical Application
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Package Footprint Compatibility
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

Over TJ = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise noted)
MINMAXUNIT

VM

Analog supply voltage

-0.3

42

V

VDD

Digital supply voltage

-0.3

5.75

V

VM_LD

Supply voltage for load dump protection

42

V

VM_SC

Supply voltage for short circuit protection

0

28

V

-VM_REV

Reverse polarity voltage, TJ(0) = 25 °C, t ≤ 2 min, RL = 70Ω on all channels

-

18

V

IVM

Current through VM pin, t ≤ 2 min

-10

10

mA

|IL|

Load current, single channel

-

IL_OCP0

A

VDS

Voltage at power FET

-0.3

42

V

VOUT_S

FET source voltage

-18

VOUT_D + 0.3

V

VOUT_D

FET drain voltage (VOUT_S ≥ 0V)

VOUT_S - 0.3

42

V

VOUT_D

FET drain voltage (VOUT_S < 0V)

-0.3

42

V

EASMaximum energy dissipation single pulse, TJ(0) = 25 °C, IL(0) = 2*IL_EAR

-

50

mJ

EASMaximum energy dissipation single pulse, TJ(0) = 150 °C, IL(0) = 400mA

-

25

mJ

EARMaximum energy dissipation for repetitive pulses -IL_EAR, 2*106 cycles, TJ(0) = 85 °C, IL(0) = IL_EAR

-

10

mJ

VI

Voltage at IN0, IN1, nSCS, SCLK, SDI pins

-0.3

5.75

V

VnSLEEP

Voltage at nSLEEP pin

-0.3

42

V

VSDOVoltage at SDO pin-0.3VDD + 0.3

V

TA

Ambient Temperature

-40

125

°C

TJ

Junction Temperature

-40

150

°C

TstgStorage temperature

-55

150

°C

  • The short circuit protection feature does not support short inductance < 1μH above 28V.

  • Load dump is for a duration of ton = 400ms; ton/toff = 10%; limited to 100 pulses.
  • For reverse polarity, TJ(0) = 25 °C, t ≤ 2 min, RL = 70Ω on all channels. Device is mounted on a FR4 2s2p board according to JEDEC JESD51-2,-5,-7 at natural convection; the Product (Chip+Package) was simulated on a 76.2 *114.3 *1.5 mm board with 2 inner copper layers (2 * 70μm Cu, 2 * 35μm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
  • For maximum energy dissipation, pulse shape represents inductive switch off: IL(t) = IL(0) x (1 - t / tpulse); 0 < t < tpulse.
  • Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
  • Fault conditions are considered as “outside” normal operating range.