SLVSFY8B February   2020  – August 2021 DRV8210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics DSG Package
    7. 7.7 Typical Characteristics DRL Package
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Control Modes
        1. 8.3.2.1 PWM Control Mode (DSG: MODE = 0 and DRL)
        2. 8.3.2.2 PH/EN Control Mode (DSG: MODE = 1)
        3. 8.3.2.3 Half-Bridge Control Mode (DSG: MODE = Hi-Z)
      3. 8.3.3 Protection Circuits
        1. 8.3.3.1 Supply Undervoltage Lockout (UVLO)
        2. 8.3.3.2 OUTx Overcurrent Protection (OCP)
        3. 8.3.3.3 Thermal Shutdown (TSD)
      4. 8.3.4 Pin Diagrams
        1. 8.3.4.1 Logic-Level Inputs
        2. 8.3.4.2 Tri-Level Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Sleep Mode
      3. 8.4.3 Fault Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Full-Bridge Driving
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Supply Voltage
          2. 9.2.1.2.2 Control Interface
          3. 9.2.1.2.3 Low-Power Operation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Half-Bridge Driving
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Supply Voltage
          2. 9.2.2.2.2 Control Interface
          3. 9.2.2.2.3 Low-Power Operation
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Coil Relay Driving
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Supply Voltage
          2. 9.2.3.2.2 Control Interface
          3. 9.2.3.2.3 Low-Power Operation
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Current Sense
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Shunt Resistor Sizing
          2. 9.2.4.2.2 RC Filter
    3. 9.3 Current Capability and Thermal Performance
      1. 9.3.1 Power Dissipation and Output Current Capability
      2. 9.3.2 Thermal Performance
        1. 9.3.2.1 Steady-State Thermal Performance
        2. 9.3.2.2 Transient Thermal Performance
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.2.2.3 Low-Power Operation

Bringing VCC to 0 V puts the DRV8210 to sleep in half-bridge mode. Section 8.4.2 describes how to enter low-power sleep mode in detail. When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power. To wake up the DRV8210 in half-bridge mode, bring VCC high, then set IN1 or IN2 high for longer than tWAKE before returning low or sending a PWM signal. Figure 9-19 and Figure 9-20 show this wakeup procedure.

Because of the decoupling capacitor on the VCC pin, TI recommends adding a resistor between the GPIO pin of the controller and the VCC pin as shown in Figure 9-9, Figure 9-10, and Figure 9-11. The purpose of this resistor is to protect the GPIO pin from large currents from the capacitor when switching the GPIO pin. However, this resistor must be sized appropriately to allow the operating current, IVCC, to flow into the VCC pin. Table 9-3 shows the design considerations for the RLIMIT resistor. VOL is the GPIO voltage when logic low, VOH is the GPIO voltage when logic high, and IOL is the maximum current that the GPIO can sink. The controller datasheet should specify VOL, VOH and IOL for the GPIO pin.

Table 9-3 GPIO pin current limiting resistor design requirements
Design consideration Equation Example
Minimum resistance needed to protect GPIO pin. Here, VCap is the voltage on the capacitor when the GPIO pin switches from high to low. To simplify calculation and assume a worst-case condition, VCap is assumed to be equivalent to the controller supply voltage, VMCU. See Figure 9-12 for example circuit. RLimit ≥ (VCap - VOL) / IOL RLimit ≥ (3.3 V - 0.3 V) / 24 mA = 125 Ω
Keep the VCC pin voltage high enough so device does not go into undervoltage lockout. See Figure 9-13 for example circuit. VOH - (IVCC × RLimit) = VVCC ≥ 1.65 V 3.0 V - (3.6 mA × 125 Ω) = 2.55 V ≥ 1.65 V
Figure 9-12 GPIO current when switching output from logic high to logic low
Figure 9-13 GPIO current with logic high output when VVCC > VVM

In cases where the specified GPIO current is too small, there are a few other options to put the device to sleep. One option is to parallel multiple GPIO to supply the appropriate current. A second option is to set MODE = IN1 = IN2 = 0 to put the device into the autosleep state. This will require the GPIO pin that controls MODE to be configured as an input during operation and an output low during sleep. A third option is to place a GPIO-controlled transistor between the supply and the VCC pin as shown in Figure 9-14.

GUID-20201208-CA0I-6XZT-W0QN-F47GNH3J6R01-low.gif Figure 9-14 GPIO with transistor

To minimize leakage current into the OUTx pins (especially in battery-powered applications), connect the load from OUTx to GND. As mentioned earlier, connecting the load from OUTx to VM is also possible, but there may be some small leakage current into OUTx when it is disabled. No leakage current is expected if loads are connected in H-bridge configuration.