SLVSG23C December   2021  – August 2022 DRV8243-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 HW Variant
      1. 6.1.1 HVSSOP (28) package
      2. 6.1.2 VQFN-HR (14) package
    2. 6.2 SPI Variant
      1. 6.2.1 HVSSOP (28) package
      2. 6.2.2 VQFN-HR (14) package
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
      1. 7.5.1  Power Supply & Initialization
      2. 7.5.2  Logic I/Os
      3. 7.5.3  SPI I/Os
      4. 7.5.4  Configuration Pins - HW Variant Only
      5. 7.5.5  Power FET Parameters
      6. 7.5.6  Switching Parameters with High-Side Recirculation
      7. 7.5.7  Switching Parameters with Low-Side Recirculation
      8. 7.5.8  IPROPI & ITRIP Regulation
      9. 7.5.9  Over Current Protection (OCP)
      10. 7.5.10 Over Temperature Protection (TSD)
      11. 7.5.11 Voltage Monitoring
      12. 7.5.12 Load Monitoring
      13. 7.5.13 Fault Retry Setting
      14. 7.5.14 Transient Thermal Impedance & Current Capability
    6. 7.6 SPI Timing Requirements
    7. 7.7 Switching Waveforms
      1. 7.7.1 Output switching transients
        1. 7.7.1.1 High-Side Recirculation
        2. 7.7.1.2 Low-Side Recirculation
      2. 7.7.2 Wake-up Transients
        1. 7.7.2.1 HW Variant
        2. 7.7.2.2 SPI Variant
      3. 7.7.3 Fault Reaction Transients
        1. 7.7.3.1 Retry setting
        2. 7.7.3.2 Latch setting
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Feature Description
      1. 8.3.1 External Components
        1. 8.3.1.1 HW Variant
        2. 8.3.1.2 SPI Variant
      2. 8.3.2 Bridge Control
        1. 8.3.2.1 PH/EN mode
        2. 8.3.2.2 PWM mode
        3. 8.3.2.3 Independent mode
        4. 8.3.2.4 Register - Pin Control - SPI Variant Only
      3. 8.3.3 Device Configuration
        1. 8.3.3.1 Slew Rate (SR)
        2. 8.3.3.2 IPROPI
        3. 8.3.3.3 ITRIP Regulation
        4. 8.3.3.4 DIAG
          1. 8.3.3.4.1 HW variant
          2. 8.3.3.4.2 SPI variant
      4. 8.3.4 Protection and Diagnostics
        1. 8.3.4.1 Over Current Protection (OCP)
        2. 8.3.4.2 Over Temperature Protection (TSD)
        3. 8.3.4.3 Off-State Diagnostics (OLP)
        4. 8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 8.3.4.5 VM Over Voltage Monitor
        6. 8.3.4.6 VM Under Voltage Monitor
        7. 8.3.4.7 Power On Reset (POR)
        8. 8.3.4.8 Event Priority
    4. 8.4 Device Functional States
      1. 8.4.1 SLEEP State
      2. 8.4.2 STANDBY State
      3. 8.4.3 Wake-up to STANDBY State
      4. 8.4.4 ACTIVE State
      5. 8.4.5 nSLEEP Reset Pulse (HW Variant Only)
    5. 8.5 Programming - SPI Variant Only
      1. 8.5.1 SPI Interface
      2. 8.5.2 Standard Frame
      3. 8.5.3 SPI Interface for Multiple Peripherals
        1. 8.5.3.1 Daisy Chain Frame for Multiple Peripherals
    6. 8.6 Register Map - SPI Variant Only
      1. 8.6.1 User Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Device Comparison

Table 5-1 summarizes the RON and package differences between devices in the DRV824X-Q1 family.

Table 5-1 Device Comparison
PART NUMBER(1) (LS + HS) RON IOUT MAX PACKAGE BODY SIZE (nominal) Variants
DRV8243-Q1 84 mΩ 12 A VQFN-HR (14) 3 mm X 4.5 mm HW (H), SPI (S)
DRV8243-Q1 98 mΩ 12 A HVSSOP (28) 3 mm X 7.3 mm HW (H), SPI (S), SPI (P)
DRV8244-Q1 47 mΩ 21 A VQFN-HR (16) 3 mm X 6 mm HW (H), SPI (S)
DRV8244-Q1 60 mΩ 21 A HVSSOP (28) 3 mm X 7.3 mm HW (H), SPI (S), SPI (P)
DRV8245-Q1 32 mΩ 32 A VQFN-HR (16) 3.5 mm X 5.5 mm HW (H), SPI (S)
DRV8245-Q1 40 mΩ 32 A HTSSOP (28) 4.4 mm X 9.7 mm HW (H), SPI (S), SPI (P)
(1) This is the product datasheet for the DRV8243-Q1. Please reference other device variant data sheets for additional information.

Table 5-2 summarizes the feature differences between the SPI and HW interface variants in the DRV824X-Q1 family. In general, the SPI variant offers more configurability, bridge control options, diagnostic feedback, redundant driver shutoff, improved Pin FMEA and additional features.

In addition, the SPI variant has two options - SPI (S) variant and SPI (P) variant. The SPI (P) variant supports an external, low voltage 5 V supply to the device through the VDD pin for the device logic, whereas in the SPI (S) variant, this supply is internally derived from the VM pin. With this external logic supply, the SPI (P) variant avoids device brown out (reset of device) during VM under voltage transients.

Table 5-2 SPI Variant vs HW Variant Comparison
FUNCTION HW (H) Variant SPI (S) Variant SPI (P) Variant
Bridge control Pin only Individual pin "and/or" register bit with pin status indication (Refer Register Pin control)
Sleep function Available through nSLEEP pin Not available
External logic supply to the device Not supported Not supported Supported through VDD pin
Clear fault command Reset pulse on nSLEEP pin SPI CLR_FAULT command
Slew rate 6 levels 8 levels
Over current protection (OCP) Fixed at the highest setting 3 choices for thresholds, 4 choices for filter time
ITRIP regulation 5 levels with disable & fixed TOFF time 7 levels with disable & indication, with programmable TOFF time
Individual fault reaction configuration between retry or latched behavior Not supported, either all latched or all retry Supported
Detailed fault logging and device status feedback Not supported, nFAULT pin monitoring necessary Supported, nFAULT pin monitoring optional
VM over voltage Fixed 4 threshold choices
On-state (Active) diagnostics Not supported Supported for high-side loads
Spread spectrum clocking (SSC) Not supported Supported
Additional driver states in PWM mode Not supported Supported
Hi-Z for individual half-bridge in Independent mode Not supported Supported (SPI register only)
Table 5-3 Differentiating between devices in the family
Device Package Symbolization DEVICE_ID Register
DRV8243H-Q1 8243H Not applicable
DRV8244H-Q1 8244H Not applicable
DRV8245H-Q1 8245H Not applicable
DRV8243S-Q1 8243S 0 x 32
DRV8244S-Q1 8244S 0 x 42
DRV8245S-Q1 8245S 0 x 52
DRV8243P-Q1 8243P 0 x 36
DRV8244P-Q1 8244P 0 x 46
DRV8245P-Q1 8245P 0 x 56