SLES267C August   2011  – March 2016 DRV8302


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Gate Timing and Protection Characteristics
    7. 6.7 Current Shunt Amplifier Characteristics
    8. 6.8 Buck Converter Characteristics
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Function Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three-Phase Gate Driver
      2. 7.3.2 Current Shunt Amplifiers
      3. 7.3.3 Buck Converter
      4. 7.3.4 Protection Features
        1. Overcurrent Protection (OCP) and Reporting
          1. Current Limit Mode (M_OC = LOW)
          2. OC Latch Shutdown Mode
        2. OC_ADJ
        3. Undervoltage Protection (UVLO)
        4. Overvoltage Protection (GVDD_OV)
        5. Overtemperature Protection
        6. Fault and Protection Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 EN_GATE
      2. 7.4.2 DTC
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Gate Driver Power Up Sequencing Errdata
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Gate Drive Average Current Load
        2. Overcurrent Protection Setup
        3. Sense Amplifier Setup
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The DRV8302 is a 8-V to 60-V, gate driver IC for three phase motor drive applications. This device reduces external component count by integrating three half-bridge drivers, two current shunt amplifiers, and a switching buck converter. The DRV8302 provides overcurrent, overtemperature, and undervoltage protection. Fault conditions are indicated through the nFAULT and nOCTW pins.

Adjustable dead time control allows for finely tuning the switching of the external MOSFETs. Internal hand shaking is used to prevent shoot-through current. VDS sensing of the external MOSFETs allows for the DRV8302 to detect overcurrent conditions and respond appropriately. The VDS trip point can be set through a hardware pin.

The highly configurable buck converter can support a wide range of output options. This allows the DRV8302 to provide a power supply rail for the controller and lower voltage components.

7.2 Function Block Diagram

DRV8302 fbd.gif

7.3 Feature Description

7.3.1 Three-Phase Gate Driver

The half-bridge drivers use a bootstrap configuration with a trickle charge pump to support 100% duty cycle operation. Each half-bridge is configured to drive two N-channel MOSFETs, one for the high-side and one for the low-side. The half-bridge drivers can be used in combination to drive a 3-phase motor or separately to drive various other loads.

The internal dead times are adjustable to accommodate a variety of external MOSFETs and applications. The dead time is adjusted with an external resistor on the DTC pin. Shorting the DTC pin to ground provides the minimum dead time (50 ns). There is an internal hand shake between the high side and low side MOSFETs during switching transitions to prevent current shoot-through.

The three-phase gate driver can provide up to 30 mA of average gate driver current. This can support switching frequencies up to 200 kHz when the MOSFET Qg = 25 nC. The high side gate drive will survive negative output from the half-bridge up to –10 V for 10 ns. During EN_GATE low and fault conditions the gate driver keeps the external MOSFETs in high impedance mode.

Each MOSFET gate driver has a VDS sensing circuit for overcurrent protection. The sense circuit measures the voltage from the drain to the source of the external MOSFETs while the MOSFET is enabled. This voltage is compared against the programmed trip point to determine if an overcurrent event has occurred. The trip voltage is set through the OC_ADJ pin with a voltage usually set with a resistor divider. The high-side sense is between the PVDD1 and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these lines helps provide accurate VDS sensing. The DRV8302 provides both cycle-by-cycle current limiting and latch overcurrent shutdown of the external MOSFET through the M_OC pin.

The DRV8302 allows for both 6-PWM and 3-PWM control through the M_PWM pin.

Table 1. 6-PWM Mode

0 0 L L
0 1 L H
1 0 H L
1 1 L L

Table 2. 3-PWM Mode

X 0 H L
X 1 L H

Table 3. Gate Driver External Components

RnOCTW nOCTW VCC (1) ≥10 kΩ
RDTC DTC GND (PowerPAD) 0 to 150 kΩ (50 ns to 500 ns)
CGVDD GVDD GND (PowerPAD) 2.2 µF (20%) ceramic, ≥ 16 V
CCP CP1 CP2 0.022 µF (20%) ceramic, rated for PVDD1
CDVDD DVDD AGND 1 µF (20%) ceramic, ≥ 6.3 V
CAVDD AVDD AGND 1 µF (20%) ceramic, ≥ 10 V
CPVDD1 PVDD1 GND (PowerPAD) ≥4.7 µF (20%) ceramic, rated for PVDD1
CBST_X BST_X SH_X 0.1 µF (20%) ceramic, ≥ 16 V
(1) VCC is the logic supply to the MCU

7.3.2 Current Shunt Amplifiers

The DRV8302 includes two high performance current shunt amplifiers to accurate low-side, inline current measurement.

The current shunt amplifiers have 2 programmable GAIN settings through the GAIN pin. These are 10, and 40 V/V.

They provide output offset up to 3 V to support bidirectional current sensing. The offset is set to half the voltage on the reference pin (REF).

To minimize DC offset and drift overtemperature, a calibration method is provided through either the DC_CAL pin. When DC calibration is enabled, the device shorts the input of the current shunt amplifier and disconnect the load. DC calibration can be done at any time, even during MOSFET switching, since the load is disconnected. For the best results, perform the DC calibration during the switching OFF period, when no load is present, to reduce the potential noise impact to the amplifier.

The output of current shunt amplifier can be calculated as:

Equation 1. DRV8302 EQ1_vo_los719.gif


  • VREF is the reference voltage (REF pin)
  • G is the gain of the amplifier (10 or 40 V/V)
  • SNX and SPx are the inputs of channel x

SPx should connect to resistor ground for the best common mode rejection.

Figure 4 shows current amplifier simplified block diagram.

DRV8302 shunt_amp_les267.gif Figure 4. Current Shunt Amplifier Simplified Block Diagram

7.3.3 Buck Converter

The DRV8302 uses an integrated TPS54160 1.5-A, 60-V, step-down DC-DC converter. Although integrated in the same device, the buck converter is designed completely independent of the rest of the gate driver circuitry. Because the buck converter can support external MCU or other external power need, the independency of buck operation is crucial for a reliable system; this gives the buck converter minimum impact from gate driver operations. Some examples are: when gate driver shuts down due to any failure, the buck still operates unless the fault is coming from the buck itself. The buck keeps operating at much lower PVDD of 3.5 V, assuring the system has a smooth power-up and power-down sequence when gate driver is not able to operate due to a low PVDD.

For proper selection of the buck converter external components, see the data sheet, TPS54160 1.5-A, 60-V, Step-Down DC/DC Converter With Eco-mode™, SLVSB56.

The buck has an integrated high-side N-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.

The wide switching frequency of 300 kHz to 2200 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT_CLK pin. The device has an internal phase lock loop (PLL) on the RT_CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock.

The buck converter has a default start-up voltage of approximately 2.5 V. The EN_BUCK pin has an internal pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN_BUCK pin is floating the device will operate. The operating current is 116 µA when not switching and under no load. When the device is disabled, the supply current is 1.3 µA.

The integrated 200-mΩ high-side MOSFET allows for high-efficiency power supply designs capable of delivering 1.5 A of continuous current to a load. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit that turns the high side MOSFET off when the boot voltage falls below a preset threshold. The buck can operate at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V reference.

The BUCK has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open-drain output that deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage, allowing the pin to transition high when a pullup resistor is used.

The BUCK minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked from turning on until the output voltage is lower than 107%.

The SS_TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power-up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor divider can be coupled to the pin for critical power supply sequencing requirements. The SS_TR pin is discharged before the output powers up. This discharging ensures a repeatable restart after an overtemperature fault,

The BUCK, also, discharges the slow-start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit slow-starts the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help control the inductor current.

Table 4. Buck Regulator External Components

RRT_CLK RT_CLK GND (PowerPAD) See Buck Converter
CCOMP COMP GND (PowerPAD) See Buck Converter
RCCOMP COMP GND (PowerPAD) See Buck Converter
RVSENSE1 PH (Filtered) VSENSE See Buck Converter
RVSENSE2 VSENSE GND (PowerPAD) See Buck Converter
LPH PH PH (Filtered) See Buck Converter
DPH PH GND (PowerPAD) See Buck Converter
CPH PH (Filtered) GND (PowerPAD) See Buck Converter
CBST_BK BST_BK PH See Buck Converter
CPVDD2 PVDD2 GND (PowerPAD) ≥4.7 µF (20%) ceramic, rated for PVDD2
CSS_TR SS_TR GND (PowerPAD) See Buck Converter
(1) VCC is the logic supply to the MCU

7.3.4 Protection Features

The DRV8302 provides a broad range of protection features and fault condition reporting. The DRV8302 has undervoltage and overtemperature protection for the IC. It also has overcurrent and undervoltage protection for the MOSFET power stage. In fault shut down conditions all gate driver outputs is held low to ensure the external MOSFETs are in a high impedance state. Overcurrent Protection (OCP) and Reporting

To protect the power stage from damage due to excessive currents, VDS sensing circuitry is implemented in the DRV8302. Based on the RDS(on) of the external MOSFETs and the maximum allowed IDS, a voltage threshold can be determined to trigger the overcurrent protection features when exceeded. The voltage threshold is programmed through the OC_ADJ pin by applying an external reference voltage with a DAC or resistor divider from DVDD. Overcurrent protection should be used as a protection scheme only; it is not intended as a precise current regulation scheme. There can be up to a 20% tolerance across channels for the VDS trip point.

Equation 2. DRV8302 qu1_sles267.gif

The VDS sense circuit measures the voltage from the drain to the source of the external MOSFET while the MOSFET is enabled. The high-side sense is between the PVDD and SH_X pins. The low-side sense is between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these lines helps provide accurate VDS sensing.

There are two different overcurrent modes that can be set through the M_OC pin. Current Limit Mode (M_OC = LOW)

In current limit mode the devices uses current limiting instead of device shutdown during an overcurrent event. After the overcurrent event, the MOSFET in which the overcurrent was detected in will shut off until the next PWM cycle. The overcurrent event will be reported through the nOCTW pin. The nOCTW pin will be held low for a maximum 64 µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered from another MOSFET, during a previous overcurrent event, the reporting will continue for another 64 µs period (internal timer will restart) or until both PWM signals cycle.

In current limit mode the device uses current limiting instead of device shutdown during an overcurrent event. In this mode the device reports overcurrent events through the nOCTW pin. The nOCTW pin will be held low for a maximum 64 µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered from another MOSFET, during a previous overcurrent event, the reporting will continue for another 64 µs period (internal timer will restart) or until both PWM signals cycle. OC Latch Shutdown Mode

When an overcurrent event occurs, both the high-side and low-side MOSFETs will be disabled in the corresponding half-bridge. The nFAULT pin will latch until the fault is reset through a quick EN_GATE reset pulse. OC_ADJ

When external MOSFET is turned on, the output current flows through the on resistance, RDS(on) of the MOSFET, which creates a voltage drop VDS. The over current protection event will be enabled when the VDS exceeds a pre-set value. The voltage on OC_ADJ pin will be used to pre-set the OC tripped value. The OC tripped value IOC has to meet following equations:

Equation 3. DRV8302 EQ2_R2_les267.gif


  • R1 + R2 ≥ 1 KΩ
  • DVDD = 3.3 V
Equation 4. DRV8302 EQ3_ioc_les267.gif

Connect OC_ADJ pin to DVDD to disable the over-current protection feature.

DRV8302 cur_prog_les267.gif Figure 5. OC_ADJ Current Programming Pin Connection Undervoltage Protection (UVLO)

To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, the DRV8302 provides undervoltage protection by driving the gate drive outputs (GH_X, GL_X) low whenever PVDD or GVDD are below their undervoltage thresholds (PVDD_UV/GVDD_UV). This will put the external MOSFETs in a high impedance state.

A specific PVDD1 undervoltage transient brownout from 13 to 15 µs can cause the DRV8302 to become unresponsive to external inputs until a full power cycle. The transient condition consists of having PVDD1 greater than the PVDD_UV level and then PVDD1 dropping below the PVDD_UV level for a specific period of 13 to 15 µs. Transients shorter or longer than 13 to 15 µs will not affect the normal operation of the undervoltage protection. Additional bulk capacitance can be added to PVDD1 to reduce undervoltage transients. Overvoltage Protection (GVDD_OV)

The device will shut down both the gate driver and charge pump if the GVDD voltage exceeds the GVDD_OV threshold to prevent potential issues related to the GVDD pin or the charge pump (For example, short of external GVDD cap or charge pump). The fault is a latched fault and can only be reset through a reset transition on the EN_GATE pin. Overtemperature Protection

A two-level overtemperature detection circuit is implemented:

  • Level 1: overtemperature warning (OTW)
    OTW is reported through nOCTW pin.
  • Level 2: overtemperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE)
    Fault will be reported to nFAULT pin. This is a latched shut down, so gate driver will not be recovered automatically even if OT condition is not present anymore. An EN_GATE reset through pin is required to recover gate driver to normal operation after temperature goes below a preset value, tOTSD_CLR. Fault and Protection Handling

The nFAULT pin indicates an error event with shut down has occurred such as over-current, overtemperature, overvoltage, or undervoltage. Note that nFAULT is an open-drain signal. nFAULT goes high when gate driver is ready for PWM signal (internal EN_GATE goes high) during start-up.

The nOCTW pin indicates an overtemperature or over current event that is not necessarily related to shut down.

Following is the summary of all protection features and their reporting structure:

Table 5. Fault and Warning Reporting and Handling

External FETs HiZ;
Weak pulldown of all gate
driver output
External FETs HiZ;
Weak pulldown of all gate
driver output; When recovering,
reset all status registers
External FETs HiZ;
Weak pulldown of all gate
driver output
External FETs HiZ;
Weak pulldown of all gate driver output
Shut down the charge pump
Won’t recover and reset through
SPI reset command or
quick EN_GATE toggling
OTW None N N Y
OTSD_GATE Gate driver latched shut down.
Weak pulldown of all gate driver output
to force external FETs HiZ
Shut down the charge pump
Buck output
UVLO_BUCK: auto-restart N Y, in PWRGD pin N
Buck overload Buck current limiting
(HiZ high side until current reaches
zero and then auto-recovering)
External FET
overload – current limit mode
External FETs current Limiting
(only OC detected FET)
External FET
overload – Latch mode
Weak pulldown of gate driver
output and PWM logic “0” of
LS and HS in the same phase.
External FETs HiZ
External FET
overload – reporting only mode
Reporting only N N Y

7.4 Device Functional Modes

7.4.1 EN_GATE

EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into a low-power consumption mode to save energy. The device will put the MOSFET output stage to high-impedance mode as long as PVDD is still present.

When the EN_GATE pin goes low to high, it goes through a power-up sequence, and enable gate driver, current amplifiers, charge pump, internal regulator, and so forth and reset all latched faults related to gate driver block. All latched faults can be reset when EN_GATE is toggled after an error event unless the fault is still present.

When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can put external FETs in high impedance mode. It will then wait for 10 µs before completely shutting down the rest of the blocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10 µs). This will prevent the device from shutting down the other functional blocks such as charge pump and internal regulators and bring a quicker and simple fault recovery. To perform a full reset, EN_GATE should be toggled for longer than 20 µs. This allows for all of the blocks to completely shut down and reach known states.

An EN_GATE reset pulse (high → low → high) from 10 to 20 µs should not be applied to the EN_GATE pin. The DRV8301 has a transition area from the quick to full reset modes that can cause the device to become unresponsive to external inputs until a full power cycle. An RC filter can be added externally to the pin if reset pulses with this period are expected to occur on the EN_GATE pin.

One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset will not work with GVDD_OV fault. A complete EN_GATE with low level holding longer than 20 µs is required to reset GVDD_OV fault. TI highly recommends inspecting the system and board when GVDD_OV occurs.

7.4.2 DTC

Dead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to control the dead time. Dead time control range is from 50 ns to 500 ns. Short DTC pin to ground provides minimum dead time (50 ns). Resistor range is 0 to 150 kΩ. Dead time is linearly set over this resistor range. Current shoot-through prevention protection will be enabled in the device all time independent of dead time setting and input mode setting.