SLVSE39B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The gate drive LS register is shown in Figure 42 and described in Table 16.
Register access type: Read/Write
10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CBC | TDRIVE | Reserved | IDRIVEP_LS | Reserved | IDRIVEN_LS | |||||
R/W-1b | R/W-11b | R/W-0b | R/W-111b | R/W-0b | R/W-111b |
Bit | Field | Type | Default | Description |
---|---|---|---|---|
10 | CBC | R/W | 1b |
In retry OCP_MODE, for both VDS_OCP and SEN_OCP, the fault is automatically cleared when a PWM input is given |
9-8 | TDRIVE | R/W | 11b |
00b = 500-ns peak gate-current drive time 01b = 1000-ns peak gate-current drive time 10b = 2000-ns peak gate-current drive time 11b = 4000-ns peak gate-current drive time |
7 | Reserved | R/W | 0b |
Reserved |
6-4 | IDRIVEP_LS | R/W | 111b |
000b = 15 mA 001b = 15 mA 010b = 45 mA 011b = 60 mA 100b = 90 mA 101b = 105 mA 110b = 135 mA 111b = 150 mA |
3 | Reserved | R/W | 0b |
Reserved |
2-0 | IDRIVEN_LS | R/W | 111b |
000b = 30 mA 001b = 30 mA 010b = 90 mA 011b = 120 mA 100b = 180 mA 101b = 210 mA 110b = 270 mA 111b = 300 mA |