SLVSD12D May   2015  – July 2019 DRV8305-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements (Slave Mode Only)
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Three-Phase Gate Driver
      2. 7.3.2 INHx/INLx: Gate Driver Input Modes
      3. 7.3.3 VCPH Charge Pump: High-Side Gate Supply
      4. 7.3.4 VCP_LSD LDO: Low-Side Gate Supply
      5. 7.3.5 GHx/GLx: Half-Bridge Gate Drivers
        1. 7.3.5.1 Smart Gate Drive Architecture: IDRIVE
        2. 7.3.5.2 Smart Gate Drive Architecture: TDRIVE
        3. 7.3.5.3 CSAs: Current Shunt Amplifiers
      6. 7.3.6 DVDD and AVDD: Internal Voltage Regulators
      7. 7.3.7 VREG: Voltage Regulator Output
      8. 7.3.8 Protection Features
        1. 7.3.8.1 Fault and Warning Classification
        2. 7.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)
        3. 7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)
          1. 7.3.8.3.1 MOSFET dV/dt Turn On Protection (TDRIVE)
          2. 7.3.8.3.2 MOSFET Gate Drive Protection (GDF)
        4. 7.3.8.4 Low-Side Source Monitors (SNS_OCP)
        5. 7.3.8.5 Fault and Warning Operating Modes
      9. 7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
        1. 7.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection
        2. 7.3.9.2 Reverse Supply Protection
        3. 7.3.9.3 MCU Watchdog
        4. 7.3.9.4 VREG Undervoltage (VREG_UV)
        5. 7.3.9.5 Latched Fault Reset Methods
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
      4. 7.4.4 Sleep State
      5. 7.4.5 Limp Home or Fail Code Operation
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 Status Registers
        1. 7.6.1.1 Warning and Watchdog Reset (Address = 0x1)
          1. Table 10. Warning and Watchdog Reset Register Description
        2. 7.6.1.2 OV/VDS Faults (Address = 0x2)
          1. Table 11. OV/VDS Faults Register Description
        3. 7.6.1.3 IC Faults (Address = 0x3)
          1. Table 12. IC Faults Register Description
        4. 7.6.1.4 VGS Faults (Address = 0x4)
          1. Table 13. Gate Driver VGS Faults Register Description
      2. 7.6.2 Control Registers
        1. 7.6.2.1 HS Gate Drive Control (Address = 0x5)
          1. Table 14. HS Gate Driver Control Register Description
        2. 7.6.2.2 LS Gate Drive Control (Address = 0x6)
          1. Table 15. LS Gate Driver Control Register Description
        3. 7.6.2.3 Gate Drive Control (Address = 0x7)
          1. Table 16. Gate Drive Control Register Description
        4. 7.6.2.4 IC Operation (Address = 0x9)
          1. Table 17. IC Operation Register Description
        5. 7.6.2.5 Shunt Amplifier Control (Address = 0xA)
          1. Table 18. Shunt Amplifier Control Register Description
        6. 7.6.2.6 Voltage Regulator Control (Address = 0xB)
          1. Table 19. Voltage Regulator Control Register Description
        7. 7.6.2.7 VDS Sense Control (Address = 0xC)
          1. Table 20. VDS Sense Control Register Description
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Drive Average Current
        2. 8.2.2.2 MOSFET Slew Rates
        3. 8.2.2.3 Overcurrent Protection
        4. 8.2.2.4 Current Sense Amplifiers
      3. 8.2.3 VREG Reference Voltage Input (DRV8305N)
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Consideration in Generator Mode
    2. 9.2 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)

To protect the system and external MOSFET from damage due to high current events, VDS overcurrent monitors are implemented in the DRV8305-Q1.

The VDS sensing is implemented for both the high-side and low-side MOSFETs through the pins below:

  • High-side MOSFET: VDS measured between VDRAIN and SHx pins.
  • Low-side MOSFET: VDS measured between SHx and SLx pins.

Based on the RDS(on) of the power MOSFETs and the maximum allowed IDS, a voltage threshold can be calculated, which when exceeded, triggers the VDS overcurrent protection feature. The voltage threshold level (VDS_LEVEL) is programmable through the SPI VDS_LEVEL setting in register 0xC, bits D7-D3 and may be changed during gate driver operation if needed.

The VDS overcurrent monitors implement adjustable blanking and deglitch times to prevent false trips due to switching voltage transients. The VDS blanking time (tBLANK) is inserted digitally and programmable through the SPI TBLANK setting in register 0x7, bits D3-D2. The tBLANK time is inserted after each switch ON transistion (LOW to HIGH) of the output gate drivers is commanded. During the tBLANK time, the VDS comparators are not being monitored in order to prevent false trips when the MOSFET first turns ON. After the tBLANK time expires the overcurrent monitors will begin actively watching for an overcurrent event.

The VDS deglitch time (tVDS) is inserted digitally and programmable through the SPI TVDS setting in register 0x7, bits D1-D0. The tVDS time is a delay inserted after the VDS sensing comparators have tripped to when the protection logic is informed that a VDS event has occurred. If the overcurrent event does not persist through tVDS delay then it will be ignored by the DRV8305-Q1.

Note that the dead time and blanking time are overlapping timers as shown in Figure 13.

DRV8305-Q1 tim_tdead_lvscx2.gifFigure 13. VDS Deglitch and Blank Diagram

The DRV8305-Q1 has three possible responses to a VDS overcurrent event. This response is set through the SPI VDS_MODE setting in register 0xC, bits D2-D0.

  • VDS Latched Shutdown Mode:

    • When a VDS overcurrent event occurs, the device will pull all gate drive outputs low in order to put all six external MOSFETs into high impedance mode. The fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was detected in reported through the SPI status registers.

  • VDS Report Only Mode:

    • In this mode, the device will take no action related to the gate drivers. When the overcurrent event is detected the fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was detected in reported through the SPI status registers. The gate drivers will continue to operate normally.

  • VDS Disabled Mode:

    • The device ignores all the VDS overcurrent event detections and does not report them.