SLVSFF3C December   2021  – October 2022 DRV8328

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 1pkg
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode
          2. 8.3.1.1.2 3x PWM Mode
        2. 8.3.1.2 Device Hardware Interface
        3. 8.3.1.3 Gate Drive Architecture
          1. 8.3.1.3.1 Propagation Delay
          2. 8.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 8.3.2 AVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Gate Driver Shutdown Sequence (DRVOFF)
      5. 8.3.5 Gate Driver Protective Circuits
        1. 8.3.5.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 8.3.5.2 AVDD Power on Reset (AVDD_POR)
        3. 8.3.5.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 8.3.5.4 BST Undervoltage Lockout (BST_UV)
        5. 8.3.5.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 8.3.5.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 8.3.5.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Three Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection
          3. 9.2.1.1.3 Gate Drive Current
          4. 9.2.1.1.4 Gate Resistor Selection
          5. 9.2.1.1.5 System Considerations in High Power Designs
            1. 9.2.1.1.5.1 Capacitor Voltage Ratings
            2. 9.2.1.1.5.2 External Power Stage Components
            3. 9.2.1.1.5.3 Parallel MOSFET Configuration
          6. 9.2.1.1.6 Dead Time Resistor Selection
          7. 9.2.1.1.7 VDSLVL Selection
          8. 9.2.1.1.8 AVDD Power Losses
          9. 9.2.1.1.9 Power Dissipation and Junction Temperature Losses
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 DRV8328A, DRV8328B RUY Package28-pin WQFN With Exposed Thermal PadTop View
Figure 6-2 DRV8328C, DRV8328D RUY Package28-pin WQFN With Exposed Thermal PadTop View
Table 6-1 Pin Functions—28-Pin DRV8328 Devices
PIN TYPE DESCRIPTION
NAME NO.
DRV8328A
DRV8328B		 DRV8328C
DRV8328D
AVDD - 19 PWR-O 3.3-V regulator output. Connect a X5R or X7R, 1-µF, >6.3-V ceramic capacitor between the AVDD and GND pins. This regulator can source up to 80 mA externally. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
BSTA 5 5 O Bootstrap output pin. Connect capacitor between BSTA and SHA
BSTB 9 9 O Bootstrap output pin. Connect capacitor between BSTB and SHB
BSTC 13 13 O Bootstrap output pin. Connect capacitor between BSTC and SHC
CPH 3 3 PWR Charge pump switching node. Connect a X5R or X7R, PVDD-rated ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
CPL 2 2 PWR
DT 27 - I Gate drive deadtime setting. Connect a resistor of value between 10 kΩ to 390 kΩ between DT and GND to adjust deadtime between 100 ns to 2000 ns. If pin is left floating or connected to GND fixed value of 55 ns deadtime is inserted.
DRVOFF - 18 I Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs by putting the gate drivers into the pull-down state. This signal bypasses and overrides the digital core of the DRV8328.
GHA 7 7 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 11 11 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 12 12 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 16 16 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 28 28 PWR Device ground.
GVDD 4 4 PWR-O Gate driver power supply output. Connect a X5R or X7R, 30-V rated ceramic ≥ 10-uF local capacitance between the GVDD and GND pins. TI recommends a capacitor value of >10x CBSTx and voltage rating at least twice the normal operating voltage of the pin.
INHA 20 22 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 19 21 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 18 20 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 23 25 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 22 24 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 21 23 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
LSS 17 17 PWR Low side source pin, connect all sources of the external low-side MOSFETs here. This pin is the sink path for the low-side gate driver.
nFAULT 24 27 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor to 3.3V to 5.0V.
nSLEEP 25 26 I Sleep mode entry pin. When this pin is pulled logic low the device goes to a low-power sleep mode. An 1 to 1.2-µs low pulse can be used to reset fault conditions without entering sleep mode .
PVDD 1 1 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, >2x PVDD-rated ceramic and >10-uF local capacitance between the PVDD and GND pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin.
SHA 6 6 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
SHB 10 10 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
SHC 14 14 I/O High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink.
VDSLVL 26 - I VDS monitor trip point setting.
Thermal Pad PWR Must be connected to GND

PWR = power, I = input, O = output, NC = no connection, OD = open-drain output