SLVSDY6A August 2018 – June 2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on). If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG deglitch time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware interface devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4 µs, and the OCP_MODE is configured for 8-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On SPI devices, the VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: VDS latched shutdown, VDS automatic retry, VDS report only, and VDS disabled.
The MOSFET VDS overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled on SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the VDS_OCP overcurrent response between linked and individual shutdown modes. When OCP_ACT is 0, a VDS_OCP fault will only effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a VDS_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.