SLOSE59C May   2020  – July 2022 DRV8424 , DRV8425

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Mixed Decay for Increasing and Decreasing Current
        4. 7.3.6.4 Smart tune Dynamic Decay
        5. 7.3.6.5 Smart tune Ripple Control
        6. 7.3.6.6 PWM OFF Time
        7. 7.3.6.7 Blanking time
      7. 7.3.7  Charge Pump
      8. 7.3.8  Linear Voltage Regulators
      9. 7.3.9  Logic Level, tri-level and quad-level Pin Diagrams
      10. 7.3.10 nFAULT Pin
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.11.3 Overcurrent Protection (OCP)
          1. 7.3.11.3.1 Latched Shutdown
          2. 7.3.11.3.2 Automatic Retry
        4. 7.3.11.4 Thermal Shutdown (OTSD)
          1. 7.3.11.4.1 Latched Shutdown
          2. 7.3.11.4.2 Automatic Retry
        5. 7.3.11.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      3. 7.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)
      4. 7.4.4 nSLEEP Reset Pulse
      5. 7.4.5 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
      4. 8.2.4 Thermal Application
        1. 8.2.4.1 Power Dissipation
          1. 8.2.4.1.1 Conduction Loss
          2. 8.2.4.1.2 Switching Loss
          3. 8.2.4.1.3 Power Dissipation Due to Quiescent Current
          4. 8.2.4.1.4 Total Power Dissipation
        2. 8.2.4.2 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, DVDD)
IVM VM operating supply current ENABLE = 1, nSLEEP = 1, No motor load 5 6.5 mA
IVMQ VM sleep mode supply current nSLEEP = 0 2 4 μA
tSLEEP Sleep time nSLEEP = 0 to sleep-mode 120 μs
tRESET nSLEEP reset pulse nSLEEP low to clear fault 20 40 μs
tWAKE Wake-up time nSLEEP = 1 to output transition 0.8 1.2 ms
tON Turn-on time VM > UVLO to output transition 0.8 1.2 ms

tEN

Enable time

ENABLE = 0/1 to output transition

5

 μs
VDVDD Internal regulator voltage No external load, 6 V < VVM < 33 V 4.75 5 5.25 V
No external load, VVM = 4.5 V

4.2

4.35

V
CHARGE PUMP (VCP, CPH, CPL)
VCP VCP operating voltage 6 V < VVM < 33 V VVM + 5 V
f(CP) Charge pump switching frequency VVM > UVLO; nSLEEP = 1 360 kHz
LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP)
VIL Input logic-low voltage 0 0.6 V
VIH Input logic-high voltage 1.5 5.5 V
VHYS Input logic hysteresis 150 mV
IIL Input logic-low current VIN = 0 V –1 1 μA
IIH Input logic-high current VIN = 5 V 100 μA
TRI-LEVEL INPUTS (M0, DECAY0, DECAY1, ENABLE)
VI1 Input logic-low voltage Tied to GND 0 0.6 V
VI2 Input Hi-Z voltage Hi-Z 1.8 2 2.2 V
VI3 Input logic-high voltage Tied to DVDD 2.7 5.5 V
IO Output pull-up current 10 μA
QUAD-LEVEL INPUTS (M1, TOFF)
VI1 Input logic-low voltage Tied to GND 0 0.6 V
VI2 330kΩ ± 5% to GND 1 1.25 1.4 V
VI3 Input Hi-Z voltage Hi-Z 1.8 2 2.2 V
VI4 Input logic-high voltage Tied to DVDD 2.7 5.5 V
IIL Output pull-up current 10 μA
CONTROL OUTPUTS (nFAULT)
VOL Output logic-low voltage IO = 5 mA 0.5 V
IOH Output logic-high leakage –1 1 μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ONH) High-side FET on resistance (DRV8424) TJ = 25 °C, IO = -1 A 165 200 mΩ
TJ = 125 °C, IO = -1 A 250 300 mΩ
TJ = 150 °C, IO = -1 A 280 350 mΩ
RDS(ONL) Low-side FET on resistance (DRV8424) TJ = 25 °C, IO = 1 A 165 200 mΩ
TJ = 125 °C, IO = 1 A 250 300 mΩ
TJ = 150 °C, IO = 1 A 280 350 mΩ
RDS(ONH) High-side FET on resistance (DRV8425) TJ = 25 °C, IO = -1 A 275 330 mΩ
TJ = 125 °C, IO = -1 A 410 500 mΩ
TJ = 150 °C, IO = -1 A 460 580 mΩ
RDS(ONL) Low-side FET on resistance (DRV8425) TJ = 25 °C, IO = 1 A 275 330 mΩ
TJ = 125 °C, IO = 1 A 410 500 mΩ
TJ = 150 °C, IO = 1 A 460 580 mΩ
tSR Output slew rate VVM = 24 V, IO = 1 A, Between 10% and 90% 240 V/µs
PWM CURRENT CONTROL (VREF)
KV Transimpedance gain VREF = 3.3 V 1.254 1.32 1.386 V/A

IVREF

VREF Leakage Current

 VREF = 3.3 V

8.25

 μA
tOFF PWM off-time TOFF = 0 7 μs
TOFF = 1 16
TOFF = Hi-Z 24
TOFF = 330 kΩ to GND 32
ΔITRIP Current trip accuracy IO = 2.5 A, 10% to 20% current setting –8 12 %
IO = 2.5 A, 20% to 40% current setting –7

7
IO = 2.5 A, 40% to 100% current setting –5 5
IO,CH AOUT and BOUT current matching IO = 2.5 A –2.5 2.5 %
PROTECTION CIRCUITS
VUVLO VM UVLO lockout VM falling, UVLO falling 4.1 4.25 4.35 V
VM rising, UVLO rising 4.2 4.35 4.45
VUVLO,HYS Undervoltage hysteresis Rising to falling threshold 100 mV
VCPUV Charge pump undervoltage VCP falling; CPUV report VVM + 2 V
IOCP Overcurrent protection Current through any FET, DRV8424 4 A
IOCP Overcurrent protection Current through any FET, DRV8425 3.2 A
tOCP Overcurrent deglitch time 1.8 μs
tRETRY Overcurrent retry time 4 ms
TOTSD Thermal shutdown Die temperature TJ 150 165 180 °C
THYS_OTSD Thermal shutdown hysteresis Die temperature TJ 20 °C