SLOSE55C May   2020  – July 2022 DRV8426

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Mixed Decay for Increasing and Decreasing Current
        4. 7.3.6.4 Smart tune Dynamic Decay
        5. 7.3.6.5 Smart tune Ripple Control
        6. 7.3.6.6 PWM OFF Time
        7. 7.3.6.7 Blanking time
      7. 7.3.7  Charge Pump
      8. 7.3.8  Linear Voltage Regulators
      9. 7.3.9  Logic Level, tri-level and quad-level Pin Diagrams
      10. 7.3.10 nFAULT Pin
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.11.3 Overcurrent Protection (OCP)
          1. 7.3.11.3.1 Latched Shutdown
          2. 7.3.11.3.2 Automatic Retry
        4. 7.3.11.4 Thermal Shutdown (OTSD)
          1. 7.3.11.4.1 Latched Shutdown
          2. 7.3.11.4.2 Automatic Retry
        5. 7.3.11.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      3. 7.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)
      4. 7.4.4 nSLEEP Reset Pulse
      5. 7.4.5 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
      4. 8.2.4 Thermal Application
        1. 8.2.4.1 Power Dissipation
          1. 8.2.4.1.1 Conduction Loss
          2. 8.2.4.1.2 Switching Loss
          3. 8.2.4.1.3 Power Dissipation Due to Quiescent Current
          4. 8.2.4.1.4 Total Power Dissipation
        2. 8.2.4.2 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Feature Description

Table 7-1 lists the recommended external components for the DRV8426 device.

Table 7-1 DRV8426 External Components
COMPONENT PIN 1 PIN 2 RECOMMENDED
CVM1 VM PGND Two X7R, 0.01-µF, VM-rated ceramic capacitors
CVM2 VM PGND Bulk, VM-rated capacitor
CCP VCP VM X7R, 0.22-µF, 16-V ceramic capacitor
CSW CPH CPL X7R, 0.022-µF, VM-rated ceramic capacitor
CDVDD DVDD GND X7R, 0.47-µF to 1-µF, 6.3-V ceramic capacitor
RnFAULT VCC (1) nFAULT >4.7-kΩ resistor
RREF1 VREF VCC Resistor to limit chopping current. It is recommended that the value of parallel combination of RREF1 and RREF2 should be less than 50-kΩ.
RREF2 (Optional) VREF GND
(1) VCC is not a pin on the DRV8426 device, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled up to DVDD.