SLES242G December   2009  – December 2014 DRV8412 , DRV8432

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Application Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Package Heat Dissipation Ratings
    6. 6.6 Package Power Deratings (DRV8412)
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Error Reporting
      2. 7.3.2 Device Protection System
        1. 7.3.2.1 Bootstrap Capacitor Undervoltage Protection
        2. 7.3.2.2 Overcurrent (OC) Protection
        3. 7.3.2.3 Overtemperature Protection
        4. 7.3.2.4 Undervoltage Protection (UVP) and Power-On Reset (POR)
      3. 7.3.3 Device Reset
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Full Bridge Mode Operation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Motor Voltage
          2. 8.2.1.2.2 Current Requirement of 12-V Power Supply
          3. 8.2.1.2.3 Voltage of Decoupling Capacitor
          4. 8.2.1.2.4 Overcurrent Threshold
          5. 8.2.1.2.5 Sense Resistor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Parallel Full Bridge Mode Operation
      3. 8.2.3 Stepper Motor Operation
      4. 8.2.4 TEC Driver
      5. 8.2.5 LED Lighting Driver
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supplies
    3. 9.3 System Power-Up and Power-Down Sequence
      1. 9.3.1 Powering Up
      2. 9.3.2 Powering Down
    4. 9.4 System Design Recommendations
      1. 9.4.1 VREG Pin
      2. 9.4.2 VDD Pin
      3. 9.4.3 OTW Pin
      4. 9.4.4 Mode Select Pin
      5. 9.4.5 Parallel Mode Operation
      6. 9.4.6 TEC Driver Application
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material Recommendation
      2. 10.1.2 Ground Plane
      3. 10.1.3 Decoupling Capacitor
      4. 10.1.4 AGND
    2. 10.2 Layout Example
      1. 10.2.1 Current Shunt Resistor
    3. 10.3 Thermal Considerations
      1. 10.3.1 DRV8412 Thermal Via Design Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

TA = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, fSw = 400 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG Voltage regulator, only used as a reference node VDD = 12 V 2.95 3.3 3.65 V
IVDD VDD supply current Idle, reset mode 9 12 mA
Operating, 50% duty cycle 10.5
IGVDD_X Gate supply current per half-bridge Reset mode 1.7 2.5 mA
Operating, 50% duty cycle 8
IPVDD_X Half-bridge X (A, B, C, or D) idle current Reset mode 0.7 1 mA
OUTPUT STAGE
RDS(on) MOSFET drain-to-source resistance, low side (LS) TJ = 25°C, GVDD = 12 V, Includes metallization bond wire and pin resistance 110 mΩ
MOSFET drain-to-source resistance, high side (HS) TJ = 25°C, GVDD = 12 V, Includes metallization bond wire and pin resistance 110
VF Diode forward voltage drop TJ = 25°C - 125°C, IO = 5 A 1 V
tR Output rise time Resistive load, IO = 5 A 14 ns
tF Output fall time Resistive load, IO = 5 A 14
tPD_ON Propagation delay when FET is on Resistive load, IO = 5 A 38
tPD_OFF Propagation delay when FET is off Resistive load, IO = 5 A 38
tDT Dead time between HS and LS FETs Resistive load, IO = 5 A 5.5
I/O PROTECTION
Vuvp,G Gate supply voltage GVDD_X undervoltage protection threshold 8.5 V
Vuvp,hyst(1) Hysteresis for gate supply undervoltage event 0.8
OTW(1) Overtemperature warning 115 125 135 °C
OTWhyst(1) Hysteresis temperature to reset OTW event 25
OTSD(1) Overtemperature shut down 150
OTE-OTWdifferential(1) OTE-OTW overtemperature detect temperature difference 25
OTSDHYST(1) Hysteresis temperature for FAULT to be released following an OTSD event 25
IOC Overcurrent limit protection Resistor—programmable, nominal, ROCP = 27 kΩ 9.7 A
IOCT Overcurrent response time Time from application of short condition to Hi-Z of affected FET(s) 250 ns
RPD Internal pulldown resistor at the output of each half-bridge Connected when RESET_AB or RESET_CD is active to provide bootstrap capacitor charge 1 kΩ
STATIC DIGITAL SPECIFICATIONS
VIH High-level input voltage PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3 2 3.6 V
VIH High-level input voltage RESET_AB, RESET_CD 2 5.5
VIL Low-level input voltage PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD 0.8
llkg Input leakage current –100 100 μA
OTW / FAULT
RINT_PU Internal pullup resistance, OTW to VREG, FAULT to VREG 20 26 35 kΩ
VOH High-level output voltage Internal pullup resistor only 2.95 3.3 3.65 V
External pullup of 4.7 kΩ to 5 V 4.5 5
VOL Low-level output voltage IO = 4 mA 0.2 0.4
Specified by design