SLES242G December   2009  – December 2014 DRV8412 , DRV8432

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Simplified Application Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Package Heat Dissipation Ratings
    6. 6.6 Package Power Deratings (DRV8412)
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Error Reporting
      2. 7.3.2 Device Protection System
        1. 7.3.2.1 Bootstrap Capacitor Undervoltage Protection
        2. 7.3.2.2 Overcurrent (OC) Protection
        3. 7.3.2.3 Overtemperature Protection
        4. 7.3.2.4 Undervoltage Protection (UVP) and Power-On Reset (POR)
      3. 7.3.3 Device Reset
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Full Bridge Mode Operation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Motor Voltage
          2. 8.2.1.2.2 Current Requirement of 12-V Power Supply
          3. 8.2.1.2.3 Voltage of Decoupling Capacitor
          4. 8.2.1.2.4 Overcurrent Threshold
          5. 8.2.1.2.5 Sense Resistor
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Parallel Full Bridge Mode Operation
      3. 8.2.3 Stepper Motor Operation
      4. 8.2.4 TEC Driver
      5. 8.2.5 LED Lighting Driver
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supplies
    3. 9.3 System Power-Up and Power-Down Sequence
      1. 9.3.1 Powering Up
      2. 9.3.2 Powering Down
    4. 9.4 System Design Recommendations
      1. 9.4.1 VREG Pin
      2. 9.4.2 VDD Pin
      3. 9.4.3 OTW Pin
      4. 9.4.4 Mode Select Pin
      5. 9.4.5 Parallel Mode Operation
      6. 9.4.6 TEC Driver Application
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material Recommendation
      2. 10.1.2 Ground Plane
      3. 10.1.3 Decoupling Capacitor
      4. 10.1.4 AGND
    2. 10.2 Layout Example
      1. 10.2.1 Current Shunt Resistor
    3. 10.3 Thermal Considerations
      1. 10.3.1 DRV8412 Thermal Via Design Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overcurrent (OC) Protection

The DRV841x2 has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. There are two settings for OC protection through mode selection pins: cycle-by-cycle (CBC) current limiting mode and OC latching (OCL) shut down mode.

In CBC current limiting mode, the detector outputs are monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing, that is, it performs a CBC current-limiting function rather than prematurely shutting down the device. This feature could effectively limit the inrush current during motor start-up or transient without damaging the device. During short to power and short to ground conditions, the current limit circuitry might not be able to control the current to a proper level, a second protection system triggers a latching shutdown, resulting in the related half bridge being set in the high-impedance (Hi-Z) state. Current limiting and overcurrent protection are independent for half-bridges A, B, C, and, D, respectively.

Figure 6 illustrates cycle-by-cycle operation with high side OC event and Figure 7 shows cycle-by-cycle operation with low side OC. Dashed lines are the operation waveforms when no CBC event is triggered and solid lines show the waveforms when CBC event is triggered. In CBC current limiting mode, when low side FET OC is detected, the device will turn off the affected low side FET and keep the high side FET at the same half bridge off until the next PWM cycle; when high side FET OC is detected, the device will turn off the affected high side FET and turn on the low side FET at the half bridge until next PWM cycle.

It is important to note that if the input to a half bridge is held to a constant value when an over current event occurs in CBC, then the associated half bridge will be in a HI-Z state upon the over current event ending. Cycling IN_X will allow OUT_X to resume normal operation.

In OC latching shut down mode, the CBC current limit and error recovery circuits are disabled and an overcurrent condition will cause the device to shutdown immediately. After shutdown, RESET_AB and/or RESET_CD must be asserted to restore normal operation after the overcurrent condition is removed.

For added flexibility, the OC threshold is programmable using a single external resistor connected between the OC_ADJ pin and GND pin. See Table 2 for information on the correlation between programming-resistor value and the OC threshold. The values in Table 2 show typical OC thresholds for a given resistor. Assuming a fixed resistance on the OC_ADJ pin across multiple devices, a 20% device-to-device variation in OC threshold measurements is possible. Therefore, this feature is designed for system protection and not for precise current control. It should be noted that a properly functioning overcurrent detector assumes the presence of a proper inductor or power ferrite bead at the power-stage output. Short-circuit protection is not guaranteed with direct short at the output pins of the power stage.

For normal operation, inductance in motor (assume larger than 10 µH) is sufficient to provide low di/dt output (for example, for EMI) and proper protection during overload condition (CBC current limiting feature). So no additional output inductors are needed during normal operation.

However during a short condition, the motor (or other load) is shorted, so the load inductance is not present in the system anymore; the current in the device can reach such a high level that may exceed the abs max current rating due to extremely low impendence in the short circuit path and high di/dt before oc detection circuit kicks in. So a ferrite bead or inductor is recommended to use the short-circuit protection feature in DRV841x2. With an external inductance or ferrite bead, the current will rise at a much slower rate and reach a lower current level before oc protection starts. The device will then either operate CBC current limit or OC shut down automatically (when current is well above the current limit threshold) to protect the system.

For a system that has limited space, a power ferrite bead can be used instead of an inductor. The current rating of ferrite bead has to be higher than the RMS current of the system at normal operation. A ferrite bead designed for very high frequency is NOT recommended. A minimum impedance of 10 Ω or higher is recommended at 10 MHz or lower frequency to effectively limit the current rising rate during short circuit condition.

The TDK MPZ2012S300A (with size of 0805 inch type) have been tested in our system to meet a short circuit condition in the DRV8412. But other ferrite beads that have similar frequency characteristics can be used as well.

For higher power applications, such as in the DRV8432, there might be limited options to select suitable ferrite bead with high current rating. If an adequate ferrite bead cannot be found, an inductor can be used.

The inductance can be calculated as:

Equation 1. DRV8412 DRV8432 eq_oi_sel_sel242.gif

where

  • Toc_delay = 250 nS
  • Ipeak = 15 A (below abs max rating)

Because an inductor usually saturates after reaching its current rating, it is recommended to use an inductor with a doubled value or an inductor with a current rating well above the operating condition.

Table 2. Programming-Resistor Values and OC Threshold

OC-ADJUST RESISTOR VALUES (kΩ) MAXIMUM CURRENT BEFORE OC OCCURS (A)
22(1) 11.6
24 10.7
27 9.7
30 8.8
36 7.4
39 6.9
43 6.3
47 5.8
56 4.9
68 4.1
82 3.4
100 2.8
120 2.4
150 1.9
200 1.4
Recommended to use in OC Latching Mode Only