SLOSE70 December   2020 DRV8434S

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Indexer Timing Requirements
      1. 6.7.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Slow Decay for Increasing Current, Fast Decay for Decreasing current
        4. 7.3.6.4 Mixed Decay for Increasing and Decreasing Current
        5. 7.3.6.5 Smart tune Dynamic Decay
        6. 7.3.6.6 Smart tune Ripple Control
      7. 7.3.7  PWM OFF Time
      8. 7.3.8  Blanking time
      9. 7.3.9  Charge Pump
      10. 7.3.10 Linear Voltage Regulators
      11. 7.3.11 Logic Level, tri-level and quad-level Pin Diagrams
        1. 7.3.11.1 nFAULT Pin
      12. 7.3.12 Protection Circuits
        1. 7.3.12.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.12.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.12.3 Overcurrent Protection (OCP)
          1. 7.3.12.3.1 Latched Shutdown (OCP_MODE = 0b)
          2. 7.3.12.3.2 Automatic Retry (OCP_MODE = 1b)
        4. 7.3.12.4 Stall Detection
        5. 7.3.12.5 Open-Load Detection (OL)
        6. 7.3.12.6 Overtemperature Warning (OTW)
        7. 7.3.12.7 Thermal Shutdown (OTSD)
          1. 7.3.12.7.1 Latched Shutdown (OTSD_MODE = 0b)
          2. 7.3.12.7.2 Automatic Recovery (OTSD_MODE = 1b)
        8.       Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2.      56
      3. 7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      4. 7.4.3 Operating Mode (nSLEEP = 1, ENABLE = 1)
      5. 7.4.4 nSLEEP Reset Pulse
      6.      Functional Modes Summary
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Target Device
        3. 7.5.1.3 SPI for Multiple Target Devices in Daisy Chain Configuration
        4. 7.5.1.4 SPI for Multiple Target Devices in Parallel Configuration
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Mode
        4. 8.2.2.4 Application Curves
        5. 8.2.2.5 Thermal Application
          1. 8.2.2.5.1 Power Dissipation
          2. 8.2.2.5.2 Conduction Loss
          3. 8.2.2.5.3 Switching Loss
          4. 8.2.2.5.4 Power Dissipation Due to Quiescent Current
          5. 8.2.2.5.5 Total Power Dissipation
          6. 8.2.2.5.6 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Register Maps

GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X1879 lists the memory-mapped registers for the DRV8434S device. All register addresses not listed in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X1879 should be considered as reserved locations and the register contents must not be modified.

Table 7-15 Memory Map
Register
Name		76543210Access
Type		Address
FAULT StatusFAULTSPI_ERRORUVLOCPUVOCPSTLTFOLR0x00
DIAG Status 1OCP_LS2_BOCP_HS2_BOCP_LS1_BOCP_HS1_BOCP_LS2_AOCP_HS2_AOCP_LS1_AOCP_HS1_AR0x01
DIAG Status 2RSVDOTWOTSSTL_LRN_OKSTALLRSVDOL_BOL_AR0x02
CTRL1TRQ_DAC [3:0]RSVDOL_MODERSVDRW0x03
CTRL2EN_OUTRSVDTOFF [1:0]DECAY [2:0]RW0x04
CTRL3DIRSTEPSPI_DIRSPI_STEPMICROSTEP_MODE [3:0]RW0x05
CTRL4CLR_FLTLOCK [2:0]EN_OLOCP_MODEOTSD_MODEOTW_REPRW0x06
CTRL5RSVDSTL_LRNEN_STLSTL_REPRSVDRW0x07
CTRL6STALL_TH [7:0]RW0x08
CTRL7RC_RIPPLE[1:0]EN_SSCTRQ_SCALESTALL_TH[11:8]RW0x09
CTRL8TRQ_COUNT [7:0]R0x0A
CTRL9REV_ID[3:0]TRQ_COUNT[11:8]R0x0B

Complex bit access types are encoded to fit into small table cells. GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#FUNC_PAD_CONTROL_LEGEND shows the codes that are used for access types in this section.

Table 7-16 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1 Status Registers

The status registers are used to reporting warning and fault conditions. Status registers are read-only registers

GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X4163 lists the memory-mapped registers for the status registers. All register offset addresses not listed in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X4163 should be considered as reserved locations and the register contents should not be modified.

Table 7-17 Status Registers Summary Table
AddressRegister NameSection
0x00FAULT statusGo
0x01DIAG status 1Go
0x02DIAG status 2Go

7.6.2 FAULT Status Register Name (address = 0x00)

FAULT status is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X1613 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X1035.

Read-only

Figure 7-31 FAULT Status Register
76543210
FAULTSPI_ERRORUVLOCPUVOCPSTLTFOL
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-18 FAULT Status Register Field Descriptions
BitFieldTypeDefaultDescription
7FAULTR0b

When nFAULT pin is at 1, FAULT bit is 0. When nFAULT pin is at 0, FAULT bit is 1.

6SPI_ERRORR0b

Indicates SPI protocol errors, such as more SCLK pulses than are required or SCLK is absent even though nSCS is low. Becomes high in fault and the nFAULT pin is driven low. Normal operation resumes when the protocol error is removed and a clear faults command has been issued either through the CLR_FLT bit or an nSLEEP reset pulse.

5UVLOR0b

Indicates an supply undervoltage lockout fault condition.

4CPUVR0b

Indicates charge pump undervoltage fault condition.

3OCPR0b

Indicates overcurrent fault condition

2STLR0b

Indicates motor stall condition.

1TFR0b

Logic OR of the overtemperature warning and overtemperature shutdown.

0OLR0b

Indicates open-load condition.

7.6.3 DIAG Status 1 (address = 0x01)

DIAG Status 1 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X3596 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X4720.

Read-only

Figure 7-32 DIAG Status 1 Register
76543210
OCP_LS2_BOCP_HS2_BOCP_LS1_BOCP_HS1_BOCP_LS2_AOCP_HS2_AOCP_LS1_AOCP_HS1_A
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-19 DIAG Status 1 Register Field Descriptions
BitFieldTypeDefaultDescription
7OCP_LS2_BR0b

Indicates overcurrent fault on the low-side FET of half bridge 2 in BOUT

6OCP_HS2_BR0b

Indicates overcurrent fault on the high-side FET of half bridge 2 in BOUT

5OCP_LS1_BR0b

Indicates overcurrent fault on the low-side FET of half bridge 1 in BOUT

4OCP_HS1_BR0b

Indicates overcurrent fault on the high-side FET of half bridge 1 in BOUT

3OCP_LS2_AR0b

Indicates overcurrent fault on the low-side FET of half bridge 2 in AOUT

2OCP_HS2_AR0b

Indicates overcurrent fault on the high-side FET of half bridge 2 in AOUT

1OCP_LS1_AR0b

Indicates overcurrent fault on the low-side FET of half bridge 1 in AOUT

0OCP_HS1_AR0b

Indicates overcurrent fault on the high-side FET of half bridge 1 in AOUT

7.6.4 DIAG Status 2 (address = 0x02)

DIAG Status 2 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X5602 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X9320.

Read-only

Figure 7-33 DIAG Status 2 Register
76543210
RSVDOTWOTSSTL_LRN_OKSTALLRSVDOL_BOL_A
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-20 DIAG Status 2 Register Field Descriptions
BitFieldTypeDefaultDescription
7RSVDR0b

Resrved.

6OTWR0b

Indicates overtemperature warning.

5OTSR0b

Indicates overtemperature shutdown.

4STL_LRN_OKR0b

Indicates stall detection learning is successful

3STALLR0b

Indicates motor stall condition

2RSVDR0b

Reserved.

1OL_BR0b

Indicates open-load detection on BOUT

0OL_AR0b

Indicates open-load detection on AOUT

7.6.5 Control Registers

The IC control registers are used to configure the device. Status registers are read and write capable.

GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X1924 lists the memory-mapped registers for the control registers. All register offset addresses not listed in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X1924 should be considered as reserved locations and the register contents should not be modified.

Table 7-21 Control Registers Summary Table
AddressRegister NameSection
0x03CTRL1GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X2549
0x04CTRL2GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X7188
0x05CTRL3GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X5700
0x06CTRL4GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X2345
0x07CTRL5GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X9661
0x08CTRL6GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X4843
0x09CTRL7GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X9501
0x0ACTRL8GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X9033
0x0BCTRL9

7.6.6 CTRL1 Control Register (address = 0x03)

CTRL1 control is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X4730 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X3531.

Read/Write

Figure 7-34 CTRL1 Control Register
76543210
TRQ_DAC [3:0]RSVDOL_MODERSVD
R/W-0000bR/W-00bR/W-0bR/W-0b
Table 7-22 CTRL1 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-4TRQ_DAC [3:0]R/W0000b

0000b = 100%

0001b = 93.75%

0010b = 87.5%

0011b = 81.25%

0100b = 75%

0101b = 68.75%

0110b = 62.5%

0111b = 56.25%

1000b = 50%

1001b = 43.75%

1010b = 37.5%

1011b = 31.25%

1100b = 25%

1101b = 18.75%

1110b = 12.5%

1111b = 6.25%

3-2RSVDR/W00b

Reserved

1OL_MODER/W0b

0b = nFAULT is released after latched OL fault is cleared using CLR_FLT bit or nSLEEP reset pulse

1b = nFAULT is released immediately after OL fault condition is removed

0RSVDR/W0b

Reserved

7.6.7 CTRL2 Control Register (address = 0x04)

CTRL2 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X5244 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X9700.

Read/Write

Figure 7-35 CTRL2 Control Register
76543210
EN_OUTRSVDTOFF [1:0]DECAY [2:0]
R/W-0bR/W-00bR/W-01bR/W-111b
Table 7-23 CTRL2 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7EN_OUTR/W0b

Write '0' to disable all outputs.

6-5RSVDR/W00b

Reserved

4-3TOFF [1:0]R/W01b

00b = 7 µs

01b = 16 µs

10b = 24 µs

11b = 32 µs

2-0DECAY [2:0]R/W111b

000b = Increasing SLOW, decreasing SLOW

001b = Increasing SLOW, decreasing MIXED 30%

010b = Increasing SLOW, decreasing MIXED 60%

011b = Increasing SLOW, decreasing FAST

100b = Increasing MIXED 30%, decreasing MIXED 30%

101b = Increasing MIXED 60%, decreasing MIXED 60%

110b = Smart tune Dynamic Decay

111b = Smart tune Ripple Control

7.6.8 CTRL3 Control Register (address = 0x05)

CTRL3 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X2253 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X4948.

Read/Write

Figure 7-36 CTRL3 Control Register
76543210
DIRSTEPSPI_DIRSPI_STEPMICROSTEP_MODE [3:0]
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0110b
Table 7-24 CTRL3 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7DIRR/W0b

Direction input. Logic '1' sets the direction of stepping, when SPI_DIR = 1.

6STEPR/W0b

Step input. Logic '1' causes the indexer to advance one step, when SPI_STEP = 1. This bit is self-clearing, automatically becomes '0' after writing '1'.

5SPI_DIRR/W0b

0b = Outputs follow input pin for DIR

1b = Outputs follow SPI registers DIR

4SPI_STEPR/W0b

0b = Outputs follow input pin for STEP

1b = Outputs follow SPI registers STEP

3-0MICROSTEP_MODE [3:0]R/W0110b

0000b = Full step (2-phase excitation) with 100% current

0001b = Full step (2-phase excitation) with 71% current

0010b = Non-circular 1/2 step

0011b = 1/2 step

0100b = 1/4 step

0101b = 1/8 step

0110b = 1/16 step

0111b = 1/32 step

1000b = 1/64 step

1001b = 1/128 step

1010b = 1/256 step

1011b to 1111b = Reserved

7.6.9 CTRL4 Control Register (address = 0x06)

CTRL4 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X6911 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X9290.

Read/Write

Figure 7-37 CTRL4 Control Register
76543210
CLR_FLTLOCK [2:0]EN_OLOCP_MODEOTSD_MODEOTW_REP
R/W-0bR/W-011bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-25 CTRL4 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7CLR_FLTR/W0b

Write '1' to this bit to clear all latched fault bits. This bit automatically resets after being written.

6-4LOCK [2:0]R/W011b

Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x06h bit 7 (CLR_FLT). Writing any sequence other than 110b has no effect when unlocked.

Write 011b to this register to unlock all registers. Writing any sequence other than 011b has no effect when locked.

3EN_OLR/W0b

Write '1' to enable open load detection

2OCP_MODER/W0b

0b = Overcurrent condition causes a latched fault

1b = Overcurrent condition causes an automatic retrying fault

1OTSD_MODER/W0b

0b = Overtemperature condition will cause latched fault

1b = Overtemperature condition will cause automatic recovery fault

0TW_REPR/W0b

0b = Overtemperature or undertemperature warning is not reported on the nFAULT line

1b = Overtemperature or undertemperature warning is reported on the nFAULT line

7.6.10 CTRL5 Control Register (address = 0x07)

CTRL5 control is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X1023 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X7803.

Read/Write

Figure 7-38 CTRL5 Control Register
76543210
RSVDSTL_LRNEN_STLSTL_REPRSVD
R/W-00bR/W-0bR/W-0bR/W-1bR/W-000b
Table 7-26 CTRL5 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-6RSVDR/W00b

Reserved. Should always be '00'.

5STL_LRNR/W0b

Write '1' to learn stall count for stall detection. This bit automatically returns to '0' when the stall learning process is complete.

4EN_STLR/W0b

0b = Stall detection is disabled

1b = Stall detection is enabled

3STL_REPR/W1b

0b = Stall detection is not reported on nFAULT

1b = Stall detection is reported on nFAULT

2-0RSVDR/W000b

Reserved. Should always be '000'.

7.6.11 CTRL6 Control Register (address = 0x08)

CTRL6 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X7854 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X3124.

Read/Write

Figure 7-39 CTRL6 Control Register
76543210
STALL_TH [7:0]
R/W-00000011b
Table 7-27 CTRL6 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-0STALL_TH [7:0]R/W00000011b

Lower 8-bits of stall threshold.

000000000000b = 0 count

XXXXXXXXXXXXb = 1 to 4094 counts

111111111111b = 4095 counts

7.6.12 CTRL7 Control Register (address = 0x09)

CTRL7 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X8998 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X312.

Read-only

Figure 7-40 CTRL7 Control Register
76543210
RC_RIPPLE[1:0]EN_SSCTRQ_SCALESTALL_TH[11:8]
R/W-00bR/W-1bR/W-0bR/W-0000b
Table 7-28 CTRL7 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-6RC_RIPPLE[1:0]R/W00b

00b = 1% ripple

01b = 2% ripple

10b = 4% ripple

11b = 6% ripple

5EN_SSCR/W1b

1b = spread-spectrum enabled

0b = spread-spectrum disabled

4TRQ_SCALER/W0b

0b = No torque count scaling is applied

1b = Torque count is scaled up by a factor of 8

3-0STALL_THR/W0000b

Upper 4-bits of stall threshold.

7.6.13 CTRL8 Control Register (address = 0x0A)

CTRL8 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X6083 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X6924.

Read-only

Figure 7-41 CTRL8 Control Register
76543210
TRQ_COUNT[7:0]
R-11111111b
Table 7-29 CTRL8 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-0TRQ_COUNTR11111111b

Lower 8-bits of TRQ_COUNT.

000000000000b = 0 count

XXXXXXXXXXXXb = 1 to 4094 counts

111111111111b = 4095 counts

7.6.14 CTRL9 Control Register (address = 0x0B)

CTRL9 is shown in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X60831 and described in GUID-8F237F41-1926-4B96-B87B-F099722C1D1B.html#X69241.

Read-only

Figure 7-42 CTRL9 Control Register
76543210
REV_ID[3:0]TRQ_COUNT[11:8]
R-0000bR-1111b
Table 7-30 CTRL9 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-4REV_IDR0000bSilicon Revision Identification. 0000b indicates Production Revision.
3-0TRQ_COUNTR1111b

Upper 4-bits of TRQ_COUNT.