SLOSE70 December 2020 DRV8434S
In addition to the CLR_FLT bit in the SPI register, a latched fault can be cleared with an nSLEEP reset pulse. This pulse width must be greater than 20 µs and lesser than 40 µs. If nSLEEP is low for longer than 40 µs but less than 120 µs, the faults are cleared and the device may or may not shutdown, as shown in the timing diagram (see Figure 7-22). This reset pulse resets any SPI faults and does not affect the status of the charge pump or other functional blocks.