SLVSDR9E October   2016  – January 2021 DRV8702-Q1 , DRV8703-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8.     15
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision D (December 2018) to Revision E (January 2021)

  • Added Functional Safety bulletGo

Changes from Revision C (August 2018) to Revision D (December 2018)

  • Changed front page to remove second descriptionGo
  • Deleted Gate-Drive Current figure Go
  • Added SL2 pin to the continous shunt amplifier input pin voltageGo
  • Added SL2 pin to the continous shunt amplifier input pin voltageGo
  • Changed IN1 to IN1/PH and IN2 to IN2/EN Go
  • Changed MODE typical pulldown resistance Go
  • Added MODE typical pullup resistanceGo
  • Changed Wording in VDS Configuration section Go

Changes from Revision B (March 2017) to Revision C (August 2018)

  • Changed the Features and Descriptions sectionsGo
  • Changed the type of the SL2 pin from O to I in the Pin Functions tableGo
  • Changed SPI parameter name conventionsGo
  • Changed the VDS(OCP) from 0.86 V to 0.96 V in the OCP Threshold Voltage graphGo
  • Changed the I(CHOP) equation in the Current Regulation and Current Chopping Configuration sectionsGo
  • Changed the current equation in the Amplifier Output (SO) sectionGo
  • Changed the description of the WD_EN bit in the IDRIVE and WD Field Descriptions tableGo

Changes from Revision A (November 2016) to Revision B (March 2017)

  • Changed the maximum voltage for AVDD from 5.7 to 5.75 in the Absolute Maximum Ratings tableGo
  • Changed maximum VSP value for GAIN_CS = 00 and GAIN_CS = 10 for the DRV8703-Q1 amplifier gain parameter in the Electrical Characteristics tableGo
  • Added the R(VDRAIN) note to the External Components tableGo
  • Changed one resistor value from 32 kΩ to 65 kΩ in the MODE Pin Block Diagram Go
  • Changed what happens when a fault condition is no longer present in the Overcurrent Protection (OCP) sectionGo
  • Deleted AV × from tthe I(CHOP) equation in the Current Chopping Configuration sectionGo

Changes from Revision * (October 2016) to Revision A (November 2016)

  • Released the full version of the data sheet Go