The dead time (t(DEAD)) is measured as the time when the SH pin is in the Hi-Z state between turning off one of the half-bridge FETs and turning on the other. For example, the output is Hi-Z between turning off the high-side FET and turning on the low-side FET.
The dead time consists of an inserted digital dead time and FET gate slewing. The DRV8702D-Q1 device has a digital dead time of approximately 240 ns. The DRV8703D-Q1 device has programmable dead-time options of 120, 240, 480, 960 ns. In addition to this digital dead time, the output is Hi-Z as long as the voltage across the GL pin to ground or GH pin to SH pin is less than the FET threshold voltage.
The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GH and GL pins) includes the observable dead time.