SLVSDX8B March   2017  – December 2018 DRV8702D-Q1 , DRV8703D-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702D-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702D-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703D-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
      1. 7.6.1 DRV8703D-Q1 Memory Map
      2. 7.6.2 Status Registers
        1. 7.6.2.1 FAULT Status Register (address = 0x00h)
          1. Table 15. FAULT Status Field Descriptions
        2. 7.6.2.2 VDS and GDF Status Register Name (address = 0x01h)
          1. Table 16. VDS and GDF Status Field Descriptions
      3. 7.6.3 Control Registers
        1. 7.6.3.1 Main Control Register Name (address = 0x02h)
          1. Table 18. Main Control Field Descriptions
        2. 7.6.3.2 IDRIVE and WD Control Register Name (address = 0x03h)
          1. Table 19. IDRIVE and WD Field Descriptions
        3. 7.6.3.3 VDS Control Register Name (address = 0x04h)
          1. Table 21. VDS Control Field Descriptions
        4. 7.6.3.4 Config Control Register Name (address = 0x05h)
          1. Table 22. Config Control Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 13.5 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
VVM VM operating voltage Gate drivers functional 5.5 45 V
Logic functional 4.5 45
IVM VM operating supply current VVM = 13.5 V; nSLEEP=1 5.5 7.5 12 mA
I(SLEEP) VM sleep mode supply current nSLEEP = 0, VVM = 13.5 V, TA = 25°C 14 µA
nSLEEP = 0, VVM = 13.5 V, TA = 125°C(1) 25
VDVDD Internal logic regulator voltage 2-mA load 3 3.3 3.5 V
30-mA load, VVM = 13.5 V 2.9 3.2 3.5
VAVDD Internal logic regulator voltage 2-mA load 4.7 5 5.3 V
30-mA load, VVM = 13.5 V 4.6 5 5.3
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage VVM = 13.5 V; IVCP = 0 to 12 mA 22.5 23.5 24.5 V
VVM = 8 V; IVCP = 0 to 10 mA 13.7 14 14.8
VVM = 5.5 V; IVCP = 0 to 8 mA 8.9 9.1 9.5
IVCP Charge-pump current capacity VVM > 13.5 V 12 mA
8 V < VVM < 13.5 V 10
5.5 V < VVM < 8 V 8
CONTROL INPUTS (IN1, IN2, nSLEEP, MODE, nSCS, SCLK, SDI)
VIL Input logic-low voltage 0 0.8 V
VIH Input logic-high voltage 1.5 5.25 V
Vhys Input logic hysteresis 100 mV
IIL Input logic-low current VIN = 0 V –5 5 µA
IIH Input logic-high current VIN = 5 V 70 µA
RPD Pulldown resistance IN1, IN2, nSLEEP, nSCS, SCLK, SDI 64 100 173 kΩ
RPD Pulldown resistance MODE 65 kΩ
RPU Pullup resistance MODE 26 kΩ
CONTROL OUTPUTS (nFAULT, WDFAULT, SDO)
VOL Output logic-low voltage IO = 2 mA 0.1 V
IOZ Output high-impedance leakage 5V pullup voltage -2 2 µA
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
VGSH High-side VGS gate drive (gate-to-source) VVM > 13.5 V; VGSH with respect to SH 10.5 11.5 V
VVM = 8 V; VGSH with respect to SH 5.7 6.8
VVM = 5.5 V; VGSH with respect to SH 3.4 4
VGSL Low-side VGS gate drive (gate-to-source) VVM > 10.5 V 10.5 V
VVM < 10.5 V VVM – 2
IDRIVE(SRC_HS) High-side peak source current
(VVM = 5.5V)		 R(IDRIVE) < 1 kΩ to GND (DRV8702D) or IDRIVE = 3’b000 (DRV8703D) 10 mA
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or IDRIVE = 3’b001 (DRV8703D) 20
R(IDRIVE) = 200 kΩ to GND (DRV8702D) or IDRIVE = 3’b010 (DRV8703D) 50
IDRIVE = 3’b011 (DRV8703D) 70
IDRIVE = 3’b100 (DRV8703D) 100
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or IDRIVE = 3’b101 (DRV8703D) 145
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b110 (DRV8703D) 190
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b111 (DRV8703D) 240
IDRIVE(SNK_HS) High-side peak sink current
(VVM = 5.5V)		 R(IDRIVE) < 1 kΩ to GND (DRV8702D) or IDRIVE = 3’b000 (DRV8703D) 20 mA
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or IDRIVE = 3’b001 (DRV8703D) 40
R(IDRIVE) = 200 kΩ to GND (DRV8702D) or IDRIVE = 3’b010 (DRV8703D) 90
IDRIVE = 3’b011 (DRV8703D) 120
IDRIVE = 3’b100 (DRV8703D) 170
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or IDRIVE = 3’b101 (DRV8703D) 250
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b110 (DRV8703D) 330
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b111 (DRV8703D) 420
IDRIVE(SRC_LS) Low-side peak source current
(VVM = 5.5V)		 R(IDRIVE) < 1 kΩ to GND (DRV8702D) or IDRIVE = 3’b000 (DRV8703D) 10 mA
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or IDRIVE = 3’b001 (DRV8703D) 20
R(IDRIVE) = 200 kΩ to GND (DRV8702D) or IDRIVE = 3’b010 (DRV8703D) 40
IDRIVE = 3’b011 (DRV8703D) 55
IDRIVE = 3’b100 (DRV8703D) 75
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or IDRIVE = 3’b101 (DRV8703D) 115
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b110 (DRV8703D) 145
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b111 (DRV8703D) 190
IDRIVE(SNK_LS) Low-side peak sink current
(VVM = 5.5V)		 R(IDRIVE) < 1 kΩ to GND (DRV8702D) or IDRIVE = 3’b000 (DRV8703D) 20 mA
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or IDRIVE = 3’b001 (DRV8703D) 40
R(IDRIVE) = 200 kΩ to GND (DRV8702D) or IDRIVE = 3’b010 (DRV8703D) 85
IDRIVE = 3’b011 (DRV8703D) 115
IDRIVE = 3’b100 (DRV8703D) 160
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or IDRIVE = 3’b101 (DRV8703D) 235
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b110 (DRV8703D) 300
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b111 (DRV8703D) 360
IDRIVE(SRC_HS) High-side peak source current
(VVM = 13.5V)		 R(IDRIVE) < 1 kΩ to GND (DRV8702D) or IDRIVE = 3’b000 (DRV8703D) 10 mA
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or IDRIVE = 3’b001 (DRV8703D) 20
R(IDRIVE) = 200 kΩ to GND (DRV8702D) or IDRIVE = 3’b010 (DRV8703D) 50
IDRIVE = 3’b011 (DRV8703D) 70
IDRIVE = 3’b100 (DRV8703D) 105
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or IDRIVE = 3’b101 (DRV8703D) 155
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b110 (DRV8703D) 210
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b111 (DRV8703D) 260
IDRIVE(SNK_HS) High-side peak sink current
(VVM = 13.5V)		 R(IDRIVE) < 1 kΩ to GND (DRV8702D) or IDRIVE = 3’b000 (DRV8703D) 20 mA
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or IDRIVE = 3’b001 (DRV8703D) 40
R(IDRIVE) = 200 kΩ to GND (DRV8702D) or IDRIVE = 3’b010 (DRV8703D) 95
IDRIVE = 3’b011 (DRV8703D) 130
IDRIVE = 3’b100 (DRV8703D) 185
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or IDRIVE = 3’b101 (DRV8703D) 265
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b110 (DRV8703D) 350
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b111 (DRV8703D) 440
IDRIVE(SRC_LS) Low-side peak source current
(VVM = 13.5V)		 R(IDRIVE) < 1 kΩ to GND (DRV8702D) or IDRIVE = 3’b000 (DRV8703D) 10 mA
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or IDRIVE = 3’b001 (DRV8703D) 20
R(IDRIVE) = 200 kΩ to GND (DRV8702D) or IDRIVE = 3’b010 (DRV8703D) 45
IDRIVE = 3’b011 (DRV8703D) 60
IDRIVE = 3’b100 (DRV8703D) 90
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or IDRIVE = 3’b101 (DRV8703D) 130
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b110 (DRV8703D) 180
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b111 (DRV8703D) 225
IDRIVE(SNK_LS) Low-side peak sink current
(VVM = 13.5V)		 R(IDRIVE) < 1 kΩ to GND (DRV8702D) or IDRIVE = 3’b000 (DRV8703D) 20 mA
R(IDRIVE) = 33 kΩ to GND (DRV8702D) or IDRIVE = 3’b001 (DRV8703D) 40
R(IDRIVE) = 200 kΩ to GND (DRV8702D) or IDRIVE = 3’b010 (DRV8703D) 95
IDRIVE = 3’b011 (DRV8703D) 125
IDRIVE = 3’b100 (DRV8703D) 180
R(IDRIVE) > 2 MΩ to GND (DRV8702D) or IDRIVE = 3’b101 (DRV8703D) 260
R(IDRIVE) = 68 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b110 (DRV8703D) 350
R(IDRIVE) = 1 kΩ to AVDD (DRV8702D) or IDRIVE = 3’b111 (DRV8703D) 430
IHOLD FET holding current Source current after tDRIVE 10 mA
Sink current after tDRIVE 40
ISTRONG FET holdoff strong pulldown GH 750 mA
GL 1000
R(OFF) FET gate holdoff resistor Pulldown GH to SH 150 kΩ
Pulldown GL to GND 150
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
VVREF VREF input rms voltage For current internal chopping 0.3(2) 3.6 V
RVREF VREF input impedance DRV8702D and DRV8703D VREF_SCL = 00 (100%) 1 MΩ
DRV8703D VREF_SCL = 2’b01, 2’b10 or 2’b11 175 kΩ
AV Amplifier gain (DRV8702D-Q1) 60 < VSP < 225 mV; VSN = GND 19.3 19.8 20.3 V/V
AV Amplifier gain (DRV8703D-Q1) GAIN_CS = 00; 10 < VSP < 450 mV; VSN = GND 9.75 10 10.25 V/V
GAIN_CS = 01; 60 < VSP < 225 mV; VSN = GND 19.3 19.8 20.3
GAIN_CS = 10; 10 < VSP < 112 mV; VSN = GND 38.4 39.4 40.4
GAIN_CS = 11; 10 < VSP < 56 mV; VSN = GND 73 78 81
VIO Input-referred offset VSP = VSN = GND 5 10 mV
VIO(DRIFT) Drift offset(2) VSP = VSN = GND 10 µV/°C
ISP SP input current VSP = 100 mV; VSN = GND –20 µA
VSO SO pin output voltage range AV × Vio 4.5 V
C(SO) Allowable SO pin capacitance 1 nF
PROTECTION CIRCUITS
V(UVLO2) VM undervoltage lockout VM falling; UVLO2 report 5.25 5.45 V
VM rising; UVLO2 recovery 5.4 5.65
V(UVLO1) Logic undervoltage lockout 4.5 V
Vhys(UVLO) VM undervoltage hysteresis Rising to falling threshold 100 mV
V(CP_UV) Charge pump undervoltage VCP falling; CPUV report VVM + 1.5 V
VCP rising; CPUV recovery VVM + 1.55
Vhys(CP_UV) CP undervoltage hysteresis Rising to falling threshold 50 mV
VDS(OCP) Overcurrent protection trip level, VDS of each external FET (DRV8702D-Q1)
High side FETs: VDRAIN – SH
Low side FETs: SH – SP		 R(VDS) < 1 kΩ to GND 0.06 V
R(VDS) = 33 kΩ to GND 0.12
R(VDS) = 200 kΩ to GND 0.24
R(VDS) > 2 MΩ to GND 0.48
R(VDS) = 68 kΩ to AVDD 0.96
R(VDS) < 1 kΩ to AVDD Disabled
VDS(OCP) Overcurrent protection trip level, VDS of each external FET (DRV8703D-Q1)
High-side FETs: VDRAIN – SH
Low-side FETs: SH – SP		 VDS_LEVEL = 3’b000 0.06 V
VDS_LEVEL = 3’b001 0.145
VDS_LEVEL = 3’b010 0.17
VDS_LEVEL = 3’b011 0.2
VDS_LEVEL = 3’b100 0.12
VDS_LEVEL = 3’b101 0.24
VDS_LEVEL = 3’b110 0.48
VDS_LEVEL = 3’b111 0.96
VSP(OCP) Overcurrent protection trip level, measured by sense amplifier VSP with respect to GND 0.8 1 1.2 V
T(OTW) Thermal warning temperature(1) Die temperature TJ 120 135 145 °C
TSD Thermal shutdown temperature(1) Die temperature TJ 150 °C
Thys Thermal shutdown hysteresis(1) Die temperature TJ 20 °C
VC(GS) Gate-drive clamping voltage Positive clamping voltage 16.3 17 17.8 V
Negative clamping voltage –1 –0.7 –0.5
(1) Ensured by design and characterization data.
(2) Operational at VVREF = 0 to approximately 0.3 V, but accuracy is degraded.