If the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (VUVLO2), both FETs in the half-bridge are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The VM_UVFL bit of the DRV8703D-Q1 device is set. The operation resumes when the VM voltage rises above the UVLO2 threshold. The nFAULT pin is released after the operation resumes but the VM_UVFL bit on the DRV8703D-Q1 device remains set until cleared by writing to the CLR_FLT bit.
The SPI settings on the DRV8703D-Q1 device are not reset by this fault even though the output drivers are disabled. The settings are maintained and internal logic remains active until the VM voltage falls below the logic undervoltage threshold (VUVLO1).