SLLSFB6A May   2020  – April 2021 DRV8705-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Descriptions
  4. 4 Revision History
  5. 5 Pin Configuration
    1.     DRV8705-Q1_RHB Package (VQFN) Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Modes
        1. 7.3.3.1 Half-Bridge Control
        2. 7.3.3.2 H-Bridge Control
        3. 7.3.3.3 Split HS and LS Solenoid Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 7.3.5 Doubler (Single-Stage) Charge Pump
      6. 7.3.6 Low-Side Differential Current Shunt Amplifier
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 7.3.7.4 Quad-Level Input (GAIN)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 7.3.8.2  Fault Reset (CLR_FLT)
        3. 7.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 7.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 7.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 7.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 7.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 7.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 7.3.8.9  Thermal Warning (OTW)
        10. 7.3.8.10 Thermal Shutdown (OTSD)
        11. 7.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 7.3.8.12 Fault Detection and Response Summary Table
    4. 7.4 Device Function Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

DRV8705-Q1_RHB Package (VQFN) Pin Functions

PINI/OTYPEDESCRIPTION
NO.NAMENAME
DRV8705S-Q1DRV8705H-Q1
1GNDI/OGroundDevice ground. Connect to system ground.
2DVDDIPowerDevice logic and digital output power supply input. Connect a 1.0-µF, 6.3-V ceramic capacitor between the DVDD and GND pins.
3nSCS—IDigitalSerial chip select. A logic low on this pin enables serial interface communication. Internal pullup resistor.
—GAINIAnalogAmplifier gain setting. 4 level input pin set by an external resistor.
4SCLK—IDigitalSerial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pulldown resistor.
—VDSIAnalogVDS monitor threshold setting. 6 level input pin set by an external resistor.
5SDI—IDigitalSerial data input. Data is captured on the falling edge of the SCLK pin. Internal pulldown resistor.
—IDRIVEIAnalogGate driver output current setting. 6 level input pin set by an external resistor.
6SDO—ODigitalSerial data output. Data is shifted out on the rising edge of the SCLK pin. Push-pull output.
—MODEIAnalogPWM input mode setting. 4 level input pin set by an external resistor.
7IN1/ENIDigitalHalf-bridge control input. See PWM modes for details. Internal pulldown.
8nHIZ1IDigitalHalf-bridge control input. See PWM modes for details. Internal pulldown.
9IN2/PHIDigitalHalf-bridge control input. See PWM modes for details. Internal pulldown.
10nHIZ2IDigitalHalf-bridge control input. See PWM modes for details. Internal pulldown.
11nSLEEPIDigitalDevice enable pin. Logic low to shutdown the device and enter sleep mode. Internal pulldown resistor.
12DRVOFFIDigitalDriver shutdown pin. Logic high to pull down both high-side and low-side gate driver output. Internal pulldown resistor.
13nFAULTODigitalFault indicator output. This pin is pulled logic low to indicate a fault condition. Open-drain output. Requires external pullup resistor.
14SOOAnalogShunt amplifier output.
15RSVD——Reserved. Connect to ground or leave disconnected.
16AREFIPowerExternal voltage reference and power supply for current sense amplifiers. Connect a 0.1-µF, 6.3-V ceramic capacitor between the AREF and AGND pins.
17AGNDI/OPowerDevice ground. Connect to system ground.
18SPIAnalogShunt amplifier positive input. Connect to positive terminal of the current shunt resistor.
19SNIAnalogShunt amplifier negative input. Connect to negative terminal of the current shunt resistor.
20GH1OAnalogHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
21SH1IAnalogHigh-side source sense input. Connect to the high-side power MOSFET source.
22GL1OAnalogLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
23SL1IAnalogLow-side MOSFET gate drive sense and power return. Connect to system ground with low impedance path to the low-side MOSFET ground return.
24SL2IAnalogLow-side MOSFET gate drive sense and power return. Connect to system ground with low impedance path to the low-side MOSFET ground return.
25GL2OAnalogLow-side gate driver output. Connect to the gate of the low-side power MOSFET.
26SH2IAnalogHigh-side source sense input. Connect to the high-side power MOSFET source.
27GH2OAnalogHigh-side gate driver output. Connect to the gate of the high-side power MOSFET.
28DRAINIAnalogBridge MOSFET drain voltage sense pin. Connect to common point of the high-side MOSFET drains.
29PVDDIPowerDevice driver power supply input. Connect to the bridge power supply. Connect a 0.1-µF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10-µF between PVDD and GND pins.
30VCPI/OPowerCharge pump output. Connect a 1-µF, 16-V ceramic capacitor between the VCP and PVDD pins.
31CPHI/OPowerCharge pump switching node. Connect a 100-nF, PVDD-rated ceramic capacitor between the CPH and CPL pins.
32CPLI/OPowerCharge pump switching node. Connect a 100-nF, PVDD-rated ceramic capacitor between the CPH and CPL pins.