SLLSFA7A July   2020  – April 2021 DRV8706-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Descriptions
  4. 4 Revision History
  5. 5 Pin Configuration
    1.     DRV8706-Q1_RHB Package (VQFN) Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Modes
        1. 7.3.3.1 Half-Bridge Control
        2. 7.3.3.2 H-Bridge Control
        3. 7.3.3.3 Split HS and LS Solenoid Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 7.3.5 Doubler (Single-Stage) Charge Pump
      6. 7.3.6 Wide Common Mode Differential Current Shunt Amplifier
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 7.3.7.4 Quad-Level Input (GAIN)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 7.3.8.2  Fault Reset (CLR_FLT)
        3. 7.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 7.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 7.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 7.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 7.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 7.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 7.3.8.9  Thermal Warning (OTW)
        10. 7.3.8.10 Thermal Shutdown (OTSD)
        11. 7.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 7.3.8.12 Fault Detection and Response Summary Table
    4. 7.4 Device Function Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
      2. 10.1.2 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 STATUS Registers

Table 7-13 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in Table 7-13 should be considered as reserved locations and the register contents should not be modified.

Table 7-13 STATUS Registers
AddressAcronymRegister NameSection
0hIC_STAT_1IC status register 1Go
1hVGS_VDS_STATVGS and VDS status registerGo
2hIC_STAT_2IC status register 2Go
3hRSVD_STATReservedGo

Complex bit access types are encoded to fit into small table cells. Table 7-14 shows the codes that are used for access types in this section.

Table 7-14 STATUS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

7.6.1.1 IC_STAT_1 Register (Address = 0h) [reset = 80h]

IC_STAT_1 is shown in Figure 7-28 and described in Table 7-15.

Return to Summary Table.

Status register with the primary IC fault bits

Figure 7-28 IC_STAT_1 Register
76543210
SPI_OKPORFAULTWARNDS_GSUVOVOT
R-1bR-1bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-15 IC_STAT_1 Register Field Descriptions
BitFieldTypeResetDescription
7SPI_OKR1bNo SPI fault is detected.

0b = One or multiple of SPI_CLK_FLT or SPI_ADR_FLT in the past frames.

1b = No SPI fault is detected

6PORR1bIndicated power-on-reset condition.

0b = No power-on-reset condition is detected.

1b = Power-on reset condition is detected.

5FAULTR0bFault indicator. Mirrors nFAULT pin.
4WARNR0bWarning indicator.
3DS_GSR0bLogic OR of VDS and VGS indicators.
2UVR0bUndervoltage indicator.
1OVR0bOvervoltage indicator.
0OTR0bLogic OR of OTW and OTSD indicators.

7.6.1.2 VGS_VDS_STAT Register (Address = 1h) [reset = 0h]

VGS_VDS_STAT is shown in Figure 7-29 and described in Table 7-16.

Return to Summary Table.

Status register with the VGS and VDS fault bits

Figure 7-29 VGS_VDS_STAT Register
76543210
VGS_H1VGS_L1VGS_H2VGS_L2VDS_H1VDS_L1VDS_H2VDS_L2
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-16 VGS_VDS_STAT Register Field Descriptions
BitFieldTypeResetDescription
7VGS_H1R0bIndicates VGS gate fault on the high-side 1 MOSFET.
6VGS_L1R0bIndicates VGS gate fault on the low-side 1 MOSFET.
5VGS_H2R0bIndicates VGS gate fault on the high-side 2 MOSFET.
4VGS_L2R0bIndicates VGS gate fault on the low-side 2 MOSFET.
3VDS_H1R0bIndicates VDS overcurrent fault on the high-side 1 MOSFET.
2VDS_L1R0bIndicates VDS overcurrent fault on the low-side 1 MOSFET.
1VDS_H2R0bIndicates VDS overcurrent fault on the high-side 2 MOSFET.
0VDS_L2R0bIndicates VDS overcurrent fault on the low-side 2 MOSFET.

7.6.1.3 IC_STAT_2 Register (Address = 2h) [reset = 10h]

IC_STAT_2 is shown in Figure 7-30 and described in Table 7-17.

Return to Summary Table.

Status register with IC undervoltage, overvoltage, and SPI fault bits

Figure 7-30 IC_STAT_2 Register
76543210
PVDD_UVPVDD_OVVCP_UVOTWOTSDRESERVEDSCLK_FLTADDR_FLT
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-17 IC_STAT_2 Register Field Descriptions
BitFieldTypeResetDescription
7PVDD_UVR0bindicates undervoltage fault on PVDD pin.
6PVDD_OVR0bIndicates overvoltage fault on PVDD pin.
5VCP_UVR0bIndicates undervoltage fault on VCP pin.
4OTWR0bIndicates overtemperature warning.
3OTSDR0bIndicates overtemperature shutdown.
2RESERVEDR0bReserved.
1SCLK_FLTR0bIndicates SPI clock (frame) fault.
0ADDR_FLTR0bIndicates SPI address fault.

7.6.1.4 RSVD_STAT Register (Address = 3h) [reset = 0h]

RSVD_STAT is shown in Figure 7-31 and described in Table 7-18.

Return to Summary Table.

Reserved status register

Figure 7-31 RSVD_STAT Register
76543210
RESERVED
R-0b
Table 7-18 RSVD_STAT Register Field Descriptions
BitFieldTypeResetDescription
7-0RESERVEDR0bReserved