SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. 8.3.2.1 Serial Peripheral Interface (SPI)
        2. 8.3.2.2 Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. 8.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 8.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 8.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 8.3.3.2 H-Bridge Control
          1. 8.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 8.3.3.3 Split HS and LS Solenoid Control
          1. 8.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. 8.3.4.1 Functional Block Diagram
        2. 8.3.4.2 Slew Rate Control (IDRIVE)
        3. 8.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 8.3.4.4 Propagation Delay Reduction (PDR)
          1. 8.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 8.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 8.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 8.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 8.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 8.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 8.3.4.6 Closed Loop Slew Time Control (STC)
          1. 8.3.4.6.1 STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. 8.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 8.3.7.2 Logic Level Push Pull Output (SDO)
        3. 8.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 8.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 8.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1. 8.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 8.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 8.3.8.3  Fault Reset (CLR_FLT)
        4. 8.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 8.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 8.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 8.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 8.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 8.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 8.3.8.10 Thermal Warning (OTW)
        11. 8.3.8.11 Thermal Shutdown (OTSD)
        12. 8.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 8.3.8.13 Watchdog Timer
        14. 8.3.8.14 Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. 8.6.3.1 DRV8718-Q1_STATUS Registers
        2. 8.6.3.2 DRV8718-Q1_CONTROL Registers
        3. 8.6.3.3 DRV8718-Q1_CONTROL_ADV Registers
        4. 8.6.3.4 DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. 8.6.4.1 DRV8714-Q1_STATUS Registers
        2. 8.6.4.2 DRV8714-Q1_CONTROL Registers
        3. 8.6.4.3 DRV8714-Q1_CONTROL_ADV Registers
        4. 8.6.4.4 DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

VQFN (RHA) 40-Pin Package and Pin Functions

GUID-4269B695-257E-44AF-AFC3-F8503CE6303C-low.gif Figure 6-3 DRV8714S-Q1 VQFN (RHA) 40-Pin Package Top View
GUID-E9629530-4C03-4F35-A6CE-2F2FEEC9EA0C-low.gif Figure 6-4 DRV8714H-Q1 VQFN (RHA) 40-Pin Package Top View
Table 6-2 VQFN (RHA) 40-Pin Package Pin Functions
PIN I/O TYPE DESCRIPTION
NO. NAME
DRV8714S-Q1 DRV8714H-Q1
1 SDI I Digital Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pulldown resistor.
IDRIVE I Analog Gate driver output current setting. 6 level input pin set by an external resistor.
2 SDO O Digital Serial data output. Data is shifted out on the rising edge of the SCLK pin. Push-pull output.
MODE I Analog Analog PWM input mode setting. 4 level input pin set by an external resistor.
3 IN1/EN1 I Digital Half-bridge and H-bridge control input. See Section 8.3.3. Internal pulldown.
4 IN2/PH1 I Digital
5 IN3/EN2 I Digital
6 IN4/PH2 I Digital
7 nSLEEP I Digital Device enable pin. Logic low to shutdown the device and enter sleep mode. Internal pulldown resistor.
8 DRVOFF/nFLT I/O Digital Multi-function pin for either driver shutdown input or fault indicator output. See Section 8.3.8. Internal pulldown resistor.
nFLT O Digital Fault indicator output. This pin is pulled logic low to indicate a fault condition. Open-drain output. Requires external pullup resistor.
9 SO1 O Analog Shunt amplifier output.
10 SO2 O Analog Shunt amplifier output.
11 BRAKE I Digital Powered off braking pin. Logic high to enable low-side gate drivers while in low-power sleep mode. See Section 8.3.8.2. Internal pulldown resistor.
12 SP1 I Analog Amplifier positive input. Connect to positive terminal of the shunt resistor.
13 SN1 I Analog Amplifier negative input. Connect to negative terminal of the shunt resistor.
14 SP2 I Analog Amplifier positive input. Connect to positive terminal of the shunt resistor.
15 SN2 I Analog Amplifier negative input. Connect to negative terminal of the shunt resistor.
16 GH1 O Analog High-side gate driver output. Connect to the gate of the high-side MOSFET.
17 SH1 I Analog High-side source sense input. Connect to the high-side MOSFET source.
18 GL1 O Analog Low-side gate driver output. Connect to the gate of the low-side MOSFET.
19 PGND1 I Analog Low-side MOSFET gate drive 1-2 sense and power return. Connect to system ground close to the device and half-bridge 1-2.
20 GL2 O Analog Low-side gate driver output. Connect to the gate of the low-side MOSFET.
21 SH2 I Analog High-side source sense input. Connect to the high-side MOSFET source.
22 GH2 O Analog High-side gate driver output. Connect to the gate of the high-side MOSFET.
23 CP2L I/O Power Charge pump switching node. Connect a 100-nF, PVDD-rated ceramic capacitor between the CP2H and CP2L pins.
24 CP2H I/O Power
25 CP1L I/O Power Charge pump switching node. Connect a 100-nF, PVDD-rated ceramic capacitor between the CP1H and CP1L pins.
26 CP1H I/O Power
27 VCP I/O Power Charge pump output. Connect a 1-µF, 16-V ceramic capacitor between the VCP and PVDD pins.
28 PVDD I Power Device driver power supply input. Connect to the bridge power supply. Connect a 0.1-µF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10-µF between PVDD and GND pins.
29 DRAIN I Analog Bridge MOSFET drain voltage sense pin. Connect to common point of the high-side MOSFET drains.
30 GH3 O Analog High-side gate driver output. Connect to the gate of the high-side MOSFET.
31 SH3 I Analog High-side source sense input. Connect to the high-side MOSFET source.
32 GL3 O Analog Low-side gate driver output. Connect to the gate of the low-side MOSFET.
33 PGND2 I Analog Low-side MOSFET gate drive 3-4 sense and power return. Connect to system ground close to the device and half-bridge 3-4.
34 GL4 O Analog Low-side gate driver output. Connect to the gate of the low-side MOSFET.
35 SH4 I Analog High-side source sense input. Connect to the high-side MOSFET source.
36 GH4 O Analog High-side gate driver output. Connect to the gate of the high-side MOSFET.
37 GND I/O Ground Device ground. Connect to system ground.
38 DVDD I Power Device logic and digital output power supply input. External voltage reference and power supply for current sense amplifiers. Recommended to connect a 1.0-µF, 6.3-V ceramic capacitor between the DVDD and GND pins.
39 nSCS I Digital Serial chip select. A logic low on this pin enables serial interface communication. Internal pullup resistor.
GAIN I Analog Amplifier gain setting. 4 level input pin set by an external resistor.
40 SCLK I Digital Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pulldown resistor.
VDS I Analog VDS monitor threshold setting. 6 level input pin set by an external resistor.