SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. Serial Peripheral Interface (SPI)
        2. Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. Half-Bridge Control Scheme With Input PWM Mapping
          1. DRV8718-Q1 Half-Bridge Control
          2. DRV8714-Q1 Half-Bridge Control
        2. H-Bridge Control
          1. DRV8714-Q1 H-Bridge Control
        3. Split HS and LS Solenoid Control
          1. DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. Functional Block Diagram
        2. Slew Rate Control (IDRIVE)
        3. Gate Drive State Machine (TDRIVE)
        4. Propagation Delay Reduction (PDR)
          1. PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. PDR Pre-Charge/Pre-Discharge Setup
          2. PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. PDR Post-Charge/Post-Discharge Setup
          3. Detecting Drive and Freewheel MOSFET
        5. Automatic Duty Cycle Compensation (DCC)
        6. Closed Loop Slew Time Control (STC)
          1. STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. Logic Level Push Pull Output (SDO)
        3. Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. Quad-Level Input (GAIN, MODE)
        5. Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1.  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2.  Low IQ Powered Off Braking (POB, BRAKE)
        3.  Fault Reset (CLR_FLT)
        4.  DVDD Logic Supply Power on Reset (DVDD_POR)
        5.  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6.  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7.  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8.  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9.  Gate Driver Fault (VGS_GDF)
        10. Thermal Warning (OTW)
        11. Thermal Shutdown (OTSD)
        12. Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. Watchdog Timer
        14. Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. DRV8718-Q1_STATUS Registers
        2. DRV8718-Q1_CONTROL Registers
        3. DRV8718-Q1_CONTROL_ADV Registers
        4. DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. DRV8714-Q1_STATUS Registers
        2. DRV8714-Q1_CONTROL Registers
        3. DRV8714-Q1_CONTROL_ADV Registers
        4. DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Gate Driver Configuration
          1. VCP Load Calculation Example
          2. IDRIVE Calculation Example
          3. tDRIVE Calculation Example
          4. Maximum PWM Switching Frequency
        2. Current Shunt Amplifier Configuration
        3. Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


The DRV871x-Q1 family of devices are highly integrated, multi-channel gate drivers intended for driving multiple motors or loads in automotive applications. The devices are tailored for automotive applications by providing a wide array of configuration and control options, MOSFET slew control, MOSFET propagation delay control, and advanced diagnostic and protection functions. The devices provide either 4 (DRV8714-Q1) or 8 (DRV8718-Q1) half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The DRV871x-Q1 family of devices reduce total system cost by integrating a high number of gate drivers, driver power supples, current shunt amplifiers, and protection monitors.

The DRV871x-Q1 family of devices support a wide array of input PWM control modes. These range from half-bridge control, H-bridge control, and grouped H-bridge control through PWM multiplexing. Recirculation and muxing schemes can be configured through the device SPI interface and input pins. This allows for the device to support different configurations of the outputs such as individual or grouped multiple motor control schemes.

The DRV871x-Q1 devices are based on a smart gate drive architecture (SGD) to reduce system cost and improve reliability. The SGD architecture optimizes dead time to avoid shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) with MOSFET slew rate control through adjustable gate drive current, improves MOSFET propagation delay and matching with an adaptive controller, and protects against drain to source and gate short circuits conditions with VDS and VGS monitors. A strong pulldown circuit helps prevent dV/dt parasitic gate coupling. The external MOSFET slew control is supported through adjustable output gate drivers. The gate driver peak source and sink current can be configured between 0.5-mA and 62-mA with an additional low current mode to achieve gate drive source and sink currents less than 0.5-mA.

The devices can operate with either 3.3-V or 5-V external controllers (MCUs). A dedicated DVDD pins allows for external power to the device digital core and the digital outputs to be referenced to the controller I/O voltage. It communicates with the external controller through an SPI bus to manage configuration settings and diagnostic feedback. The device also has an AREF pin which allows for the shunt amplifier reference voltage to be connected to the reference voltage of the external controller ADC. The shunt amplifier outputs are also clamped to the AREF pin voltage to protect the inputs of the controller from excessive voltage spikes.

The devices provides an array of diagnostic and protection features to monitor system status before operation and protect against faults during system operation. These include under and overvoltage monitors for the power supply and charge pump, VDS overcurrent and VGS gate fault monitors for the external MOSFETs, offline open load and short circuit detection, windowed watchdog timer for SPI and MCI diagnostics, and internal thermal warning and shutdown protection. The current shunt amplifier can be utilized to monitor load current of the system. The high common mode range of the amplifier allows for either inline, high-side, or low-side based shunt resistor current sensing.

Lastly, the device has a unique power off braking function that gives the ability to enables the low-side drivers during the device's low-power sleep mode in case of detecting a system overvoltage condition. This can be utilized to prevent motor back-emf from overcharging the system voltage rail.