SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. 8.3.2.1 Serial Peripheral Interface (SPI)
        2. 8.3.2.2 Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. 8.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 8.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 8.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 8.3.3.2 H-Bridge Control
          1. 8.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 8.3.3.3 Split HS and LS Solenoid Control
          1. 8.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. 8.3.4.1 Functional Block Diagram
        2. 8.3.4.2 Slew Rate Control (IDRIVE)
        3. 8.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 8.3.4.4 Propagation Delay Reduction (PDR)
          1. 8.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 8.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 8.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 8.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 8.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 8.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 8.3.4.6 Closed Loop Slew Time Control (STC)
          1. 8.3.4.6.1 STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. 8.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 8.3.7.2 Logic Level Push Pull Output (SDO)
        3. 8.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 8.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 8.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1. 8.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 8.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 8.3.8.3  Fault Reset (CLR_FLT)
        4. 8.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 8.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 8.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 8.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 8.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 8.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 8.3.8.10 Thermal Warning (OTW)
        11. 8.3.8.11 Thermal Shutdown (OTSD)
        12. 8.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 8.3.8.13 Watchdog Timer
        14. 8.3.8.14 Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. 8.6.3.1 DRV8718-Q1_STATUS Registers
        2. 8.6.3.2 DRV8718-Q1_CONTROL Registers
        3. 8.6.3.3 DRV8718-Q1_CONTROL_ADV Registers
        4. 8.6.3.4 DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. 8.6.4.1 DRV8714-Q1_STATUS Registers
        2. 8.6.4.2 DRV8714-Q1_CONTROL Registers
        3. 8.6.4.3 DRV8714-Q1_CONTROL_ADV Registers
        4. 8.6.4.4 DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Smart Gate Driver

The DRV871x-Q1 provides an advanced, adjustable floating smart gate driver architecture to provide fine MOSFET control and robust switching performance. The DRV871x-Q1 provides driver functions for slew rate control and a driver state machine for dead-time handshaking, parasitic dV/dt gate coupling prevention, and MOSFET gate fault detection.

Advanced adaptive drive functions are provided for reducing propagation delay, reducing duty cycle distortion, and closed loop programmable slew time. The advanced smart gate driver functions are only available in the Half-Bridge Control PWM mode and on SPI device variants. The advanced functions do not interfere with standard operation of the gate drivers and can be utilized as needed by system requirements.

The different functions of the smart gate drive architecture are summarized below with additional details in the following sections.

Smart Gate Driver Core Functions:

Note: The advanced, adaptive drive functions and registers are not required for normal operation of the device and intended for specific system requirements.
Table 8-15 Smart Gate Driver Terminology Descriptions
Core Function Terminology Description
IDRIVE / TDRIVE IDRVP Programmable gate drive source current for adjustable MOSFET slew rate control. Configured with the IDRVP_x control register or IDRIVE pin.
IDRVN Programmable gate drive sink current for adjustable MOSFET slew rate control. Configured with the IDRVN_x control register or IDRIVE pin.
IHOLD Fixed gate driver hold pull up current during non-switching period.
ISTRONG Fixed gate driver strong pull down current during non-switching period.
tDRIVE IDRVP/N drive current duration before IHOLD or ISTRONG. Also provides VGS and VDS fault monitor blanking period. Configured with the VGS_TDRV_x control register.
tPD Propagation delay from logic control signal to gate driver output change.
tDEAD Body diode conduction period between high-side and low-side switch transition. Configured with the VGS_TDEAD_x control register.
PDR
(Pre-charge)
ICHR_INIT Gate drive source current initial value for charge control loop. Configured with the PRE_CHR_INIT_xx control register
IPRE_CHR Gate drive source current for pre-charge period after control loop lock. Adjustment rate configured with the KP_PDR_x control register. Max current clamp configured with the PRE_MAX_x control register.
tPRE_CHR Gate drive source current pre-charge period duration. Configured with the T_PRE_CHR_x control register.
tDON Delay time from start of pre-charge period to rising VSH crossing VSH_L threshold. Configure with T_DON_DOFF_x control register.
IDCHR_INIT Gate drive sink current initial value for discharge period control loop. Configured with the PRE_DCHR_INIT_x control register.
IPRE_DCHR Gate drive sink current for pre-discharge period after control loop lock. Adjustment rate configured with the KP_PDR_x control register. Max current clamp configured with the PRE_MAX_x control register.
tPRE_DCHR Gate drive sink current pre-discharge period duration. Configured with the T_PRE_DCHR_x control register.
tDOFF Delay time from start of pre-discharge period to falling VSH crossing VSH_H threshold. Configure with T_DON_DOFF_x control register.
VSH_L Low voltage threshold for VSH switch-node. Configured with the AGD_THR control register.
VSH_H High voltage threshold for VSH switch-node. Configured with the AGD_THR control register.
PDR
(Post-charge)
IPST_CHR Gate drive source current for post-charge period. Adjustment rate configured with the KP_PST_x control register.
tPST_CHR Gate drive source current post-charge period duration.
IPST_DCHR Gate drive sink current for post-discharge period. Adjustment rate configured with the KP_PST_x control register.
tPST_DCHR Gate drive source current post-charge period duration.
IFW_CHR Freewheeling charge current. Configured with the FW_MAX_x control register.
IFW_DCHR Freewheeling discharge current. Configured with the FW_MAX_x control register.
STC tRISE Time duration for VSHx to cross from VSHx_L to VSHx_H threshold. Configured with the T_RISE_FALL_x control register.
tFALL Time duration for VSHx to cross from VSHx_H to VSHx_L threshold. Configured with the T_RISE_FALL_x control register.