SLVSEA2B August   2020  – June 2021 DRV8714-Q1 , DRV8718-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1. 6.1 VQFN (RVJ) 56-Pin Package and Pin Functions
    2. 6.2 VQFN (RHA) 40-Pin Package and Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Device Interface Variants
        1. 8.3.2.1 Serial Peripheral Interface (SPI)
        2. 8.3.2.2 Hardware (H/W)
      3. 8.3.3 Input PWM Control Modes
        1. 8.3.3.1 Half-Bridge Control Scheme With Input PWM Mapping
          1. 8.3.3.1.1 DRV8718-Q1 Half-Bridge Control
          2. 8.3.3.1.2 DRV8714-Q1 Half-Bridge Control
        2. 8.3.3.2 H-Bridge Control
          1. 8.3.3.2.1 DRV8714-Q1 H-Bridge Control
        3. 8.3.3.3 Split HS and LS Solenoid Control
          1. 8.3.3.3.1 DRV8714-Q1 Split HS and LS Solenoid Control
      4. 8.3.4 Smart Gate Driver
        1. 8.3.4.1 Functional Block Diagram
        2. 8.3.4.2 Slew Rate Control (IDRIVE)
        3. 8.3.4.3 Gate Drive State Machine (TDRIVE)
        4. 8.3.4.4 Propagation Delay Reduction (PDR)
          1. 8.3.4.4.1 PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 8.3.4.4.1.1 PDR Pre-Charge/Pre-Discharge Setup
          2. 8.3.4.4.2 PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 8.3.4.4.2.1 PDR Post-Charge/Post-Discharge Setup
          3. 8.3.4.4.3 Detecting Drive and Freewheel MOSFET
        5. 8.3.4.5 Automatic Duty Cycle Compensation (DCC)
        6. 8.3.4.6 Closed Loop Slew Time Control (STC)
          1. 8.3.4.6.1 STC Control Loop Setup
      5. 8.3.5 Tripler (Dual-Stage) Charge Pump
      6. 8.3.6 Wide Common-Mode Current Shunt Amplifiers
      7. 8.3.7 Pin Diagrams
        1. 8.3.7.1 Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
        2. 8.3.7.2 Logic Level Push Pull Output (SDO)
        3. 8.3.7.3 Logic Level Multi-Function Pin (DRVOFF/nFLT)
        4. 8.3.7.4 Quad-Level Input (GAIN, MODE)
        5. 8.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 8.3.8 Protection and Diagnostics
        1. 8.3.8.1  Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
        2. 8.3.8.2  Low IQ Powered Off Braking (POB, BRAKE)
        3. 8.3.8.3  Fault Reset (CLR_FLT)
        4. 8.3.8.4  DVDD Logic Supply Power on Reset (DVDD_POR)
        5. 8.3.8.5  PVDD Supply Undervoltage Monitor (PVDD_UV)
        6. 8.3.8.6  PVDD Supply Overvoltage Monitor (PVDD_OV)
        7. 8.3.8.7  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        8. 8.3.8.8  MOSFET VDS Overcurrent Protection (VDS_OCP)
        9. 8.3.8.9  Gate Driver Fault (VGS_GDF)
        10. 8.3.8.10 Thermal Warning (OTW)
        11. 8.3.8.11 Thermal Shutdown (OTSD)
        12. 8.3.8.12 Offline Short Circuit and Open Load Detection (OOL and OSC)
        13. 8.3.8.13 Watchdog Timer
        14. 8.3.8.14 Fault Detection and Response Summary Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Inactive or Sleep State
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
    5. 8.5 Programming
      1. 8.5.1 SPI Interface
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Maps
      1. 8.6.1 DRV8718-Q1 Register Map
      2. 8.6.2 DRV8714-Q1 Register Map
      3. 8.6.3 DRV8718-Q1 Register Descriptions
        1. 8.6.3.1 DRV8718-Q1_STATUS Registers
        2. 8.6.3.2 DRV8718-Q1_CONTROL Registers
        3. 8.6.3.3 DRV8718-Q1_CONTROL_ADV Registers
        4. 8.6.3.4 DRV8718-Q1_STATUS_ADV Registers
      4. 8.6.4 DRV8714-Q1 Register Descriptions
        1. 8.6.4.1 DRV8714-Q1_STATUS Registers
        2. 8.6.4.2 DRV8714-Q1_CONTROL Registers
        3. 8.6.4.3 DRV8714-Q1_CONTROL_ADV Registers
        4. 8.6.4.4 DRV8714-Q1_STATUS_ADV Registers
  9. Application Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Driver Configuration
          1. 9.2.2.1.1 VCP Load Calculation Example
          2. 9.2.2.1.2 IDRIVE Calculation Example
          3. 9.2.2.1.3 tDRIVE Calculation Example
          4. 9.2.2.1.4 Maximum PWM Switching Frequency
        2. 9.2.2.2 Current Shunt Amplifier Configuration
        3. 9.2.2.3 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Initialization
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device Documentation and Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

DRV8718-Q1_CONTROL_ADV Registers

Table 8-68 lists the DRV8718-Q1_CONTROL_ADV registers. All register offset addresses not listed in Table 8-68 should be considered as reserved locations and the register contents should not be modified.

Table 8-68 DRV8718-Q1_CONTROL_ADV Registers
Address Acronym Register Name Section
2Ah AGD_CTRL1 Adaptive gate drive general control functions Go
2Bh PDR_CTRL1 Half-bridge 1 and 2 PDR delay and max current settings Go
2Ch PDR_CTRL2 Half-bridge 3 and 4 PDR delay and max current settings Go
2Dh PDR_CTRL3 Half-bridge 5 and 6 PDR delay and max current settings Go
2Eh PDR_CTRL4 Half-bridge 7 and 8 PDR delay and max current settings Go
2Fh PDR_CTRL5 Half-bridge 1 and 2 PDR charge and discharge initial settings. Go
30h PDR_CTRL6 Half-bridge 3 and 4 PDR charge and discharge initial settings. Go
31h PDR_CTRL7 Half-bridge 5 and 6 PDR charge and discharge initial settings. Go
32h PDR_CTRL8 Half-bridge 7 and 8 PDR charge and discharge initial settings. Go
33h PDR_CTRL9 Half-bridge 1-4 PDR loop controller gain Go
34h PDR_CTRL10 Half-bridge 5-8 PDR loop controller gain Go
35h STC_CTRL1 Half-bridge 1 and 2 STC rise/fall time and controller gain Go
36h STC_CTRL2 Half-bridge 3 and 4 STC rise/fall time and controller gain Go
37h STC_CTRL3 Half-bridge 5 and 6 STC rise/fall time and controller gain Go
38h STC_CTRL4 Half-bridge 7 and 8 STC rise/fall time and controller gain Go
39h DCC_CTRL1 Half-bridge 1-8 DCC enable and manual control Go
3Ah PST_CTRL1 Half-bridge 1-8 freewheel and post charge delay control Go
3Bh PST_CTRL2 Half-bridge 1-8 post charge controller gain Go

Complex bit access types are encoded to fit into small table cells. Table 8-69 shows the codes that are used for access types in this section.

Table 8-69 DRV8718-Q1_CONTROL_ADV Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
- n Value after reset or the default value

6.3.3.1 AGD_CTRL1 Register (Address = 2Ah) [Reset = 40h]

AGD_CTRL1 is shown in Figure 8-77 and described in Table 8-70.

Return to the Summary Table.

Control register for adaptive gate drive voltage thresholds, pull down setting, and active half-bridge configuration.

Figure 8-77 AGD_CTRL1 Register
7 6 5 4 3 2 1 0
AGD_THR AGD_ISTRONG SET_AGD_12 SET_AGD_34 SET_AGD_56 SET_AGD_78
R/W-01b R/W-00b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-70 AGD_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-6 AGD_THR R/W 01b Adaptive gate driver VSH threshold configuration.
00b = 1V, VDRAIN - 0.5V
01b = 1V, VDRAIN - 1V
10b = 2V, VDRAIN - 1.5V
11b = 2V, VDRAIN - 2V
5-4 AGD_ISTRONG R/W 00b Adaptive gate driver ISTRONG configuration.
00b = ISTRONG pulldown decoded from initial IDRVP_x register setting.
01b = 62 mA
10b = 124 mA
11b = RSVD
3 SET_AGD_12 R/W 0b Set active half-bridge for adaptive gate drive control loops.
0b = Half-bridge 1
1b = Half-bridge 2
2 SET_AGD_34 R/W 0b Set active half-bridge for adaptive gate drive control loops.
0b = Half-bridge 3
1b = Half-bridge 4
1 SET_AGD_56 R/W 0b Set active half-bridge for adaptive gate drive control loops.
0b = Half-bridge 5
1b = Half-bridge 6
0 SET_AGD_78 R/W 0b Set active half-bridge for adaptive gate drive control loops.
0b = Half-bridge 7
1b = Half-bridge 8

6.3.3.2 PDR_CTRL1 Register (Address = 2Bh) [Reset = Ah]

PDR_CTRL1 is shown in Figure 8-78 and described in Table 8-71.

Return to the Summary Table.

Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridges 1 and 2.

Figure 8-78 PDR_CTRL1 Register
7 6 5 4 3 2 1 0
PRE_MAX_12 T_DON_DOFF_12
R/W-00b R/W-001010b
Table 8-71 PDR_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-6 PRE_MAX_12 R/W 00b Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 1 and 2.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
5-0 T_DON_DOFF_12 R/W 001010b On and off time delay for half-bridge 1 and 2. 140 ns x T_DON_DOFF_12 [3:0] Default time: 001010b (1.4 us)

6.3.3.3 PDR_CTRL2 Register (Address = 2Ch) [Reset = Ah]

PDR_CTRL2 is shown in Figure 8-79 and described in Table 8-72.

Return to the Summary Table.

Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridges 3 and 4.

Figure 8-79 PDR_CTRL2 Register
7 6 5 4 3 2 1 0
PRE_MAX_34 T_DON_DOFF_34
R/W-00b R/W-001010b
Table 8-72 PDR_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-6 PRE_MAX_34 R/W 00b Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 3 and 4.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
5-0 T_DON_DOFF_34 R/W 001010b On and off time delay for half-bridge 3 and 4. 140 ns x T_DON_DOFF_34 [3:0] Default time: 001010b (1.4 us)

6.3.3.4 PDR_CTRL3 Register (Address = 2Dh) [Reset = Ah]

PDR_CTRL3 is shown in Figure 8-80 and described in Table 8-73.

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Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridges 5 and 6.

Figure 8-80 PDR_CTRL3 Register
7 6 5 4 3 2 1 0
PRE_MAX_56 T_DON_DOFF_56
R/W-00b R/W-001010b
Table 8-73 PDR_CTRL3 Register Field Descriptions
Bit Field Type Reset Description
7-6 PRE_MAX_56 R/W 00b Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 5 and 6.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
5-0 T_DON_DOFF_56 R/W 001010b On and off time delay for half-bridge 5 and 6. 140 ns x T_DON_DOFF_56 [3:0] Default time: 001010b (1.4 us)

6.3.3.5 PDR_CTRL4 Register (Address = 2Eh) [Reset = Ah]

PDR_CTRL4 is shown in Figure 8-81 and described in Table 8-74.

Return to the Summary Table.

Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridges 7 and 8.

Figure 8-81 PDR_CTRL4 Register
7 6 5 4 3 2 1 0
PRE_MAX_78 T_DON_DOFF_78
R/W-00b R/W-001010b
Table 8-74 PDR_CTRL4 Register Field Descriptions
Bit Field Type Reset Description
7-6 PRE_MAX_78 R/W 00b Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 7 and 8.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
5-0 T_DON_DOFF_78 R/W 001010b On and off time delay for half-bridge 7 and 8. 140 ns x T_DON_DOFF_78 [3:0] Default time: 001010b (1.4 us)

6.3.3.6 PDR_CTRL5 Register (Address = 2Fh) [Reset = F6h]

PDR_CTRL5 is shown in Figure 8-82 and described in Table 8-75.

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Control register for charge and pre-charge initial settings for half-bridges 1 and 2.

Figure 8-82 PDR_CTRL5 Register
7 6 5 4 3 2 1 0
T_PRE_CHR_12 T_PRE_DCHR_12 PRE_CHR_INIT_12 PRE_DCHR_INIT_12
R/W-11b R/W-11b R/W-01b R/W-10b
Table 8-75 PDR_CTRL5 Register Field Descriptions
Bit Field Type Reset Description
7-6 T_PRE_CHR_12 R/W 11b PDR control loop pre-charge time for half-bridge 1 and 2. Set as ratio of T_DON_DOFF_12 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4 T_PRE_DCHR_12 R/W 11b PDR control loop pre-discharge time for half-bridge 1 and 2. Set as ratio of T_DON_DOFF_12 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2 PRE_CHR_INIT_12 R/W 01b PDR control loop initial pre-charge current setting for half-bridge 1 and 2.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0 PRE_DCHR_INIT_12 R/W 10b PDR control loop initial pre-discharge current setting for half-bridge 1 and 2..
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

6.3.3.7 PDR_CTRL6 Register (Address = 30h) [Reset = F6h]

PDR_CTRL6 is shown in Figure 8-83 and described in Table 8-76.

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Control register for charge and pre-charge initial settings for half-bridges 3 and 4.

Figure 8-83 PDR_CTRL6 Register
7 6 5 4 3 2 1 0
T_PRE_CHR_34 T_PRE_DCHR_34 PRE_CHR_INIT_34 PRE_DCHR_INIT_34
R/W-11b R/W-11b R/W-01b R/W-10b
Table 8-76 PDR_CTRL6 Register Field Descriptions
Bit Field Type Reset Description
7-6 T_PRE_CHR_34 R/W 11b PDR control loop pre-charge time for half-bridge 3 and 4. Set as ratio of T_DON_DOFF_34 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4 T_PRE_DCHR_34 R/W 11b PDR control loop pre-discharge time for half-bridge 3 and 4. Set as ratio of T_DON_DOFF_34 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2 PRE_CHR_INIT_34 R/W 01b PDR control loop initial pre-charge current setting for half-bridge 3 and 4.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0 PRE_DCHR_INIT_34 R/W 10b PDR control loop initial pre-discharge current setting for half-bridge 3 and 4.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

6.3.3.8 PDR_CTRL7 Register (Address = 31h) [Reset = F6h]

PDR_CTRL7 is shown in Figure 8-84 and described in Table 8-77.

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Control register for charge and pre-charge initial settings for half-bridges 5 and 6.

Figure 8-84 PDR_CTRL7 Register
7 6 5 4 3 2 1 0
T_PRE_CHR_56 T_PRE_DCHR_56 PRE_CHR_INIT_56 PRE_DCHR_INIT_56
R/W-11b R/W-11b R/W-01b R/W-10b
Table 8-77 PDR_CTRL7 Register Field Descriptions
Bit Field Type Reset Description
7-6 T_PRE_CHR_56 R/W 11b PDR control loop pre-charge time for half-bridge 5 and 6. Set as ratio of T_DON_DOFF_56 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4 T_PRE_DCHR_56 R/W 11b PDR control loop pre-discharge time for half-bridge 5 and 6. Set as ratio of T_DON_DOFF_56 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2 PRE_CHR_INIT_56 R/W 01b PDR control loop initial pre-charge current setting for half-bridge 5 and 6.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0 PRE_DCHR_INIT_56 R/W 10b PDR control loop initial pre-discharge current setting for half-bridge 5 and 6.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

6.3.3.9 PDR_CTRL8 Register (Address = 32h) [Reset = F6h]

PDR_CTRL8 is shown in Figure 8-85 and described in Table 8-78.

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Control register for charge and pre-charge initial settings for half-bridges 7 and 8.

Figure 8-85 PDR_CTRL8 Register
7 6 5 4 3 2 1 0
T_PRE_CHR_78 T_PRE_DCHR_78 PRE_CHR_INIT_78 PRE_DCHR_INIT_78
R/W-11b R/W-11b R/W-01b R/W-10b
Table 8-78 PDR_CTRL8 Register Field Descriptions
Bit Field Type Reset Description
7-6 T_PRE_CHR_78 R/W 11b PDR control loop pre-charge time for half-bridge 7 and 8. Set as ratio of T_DON_DOFF_78 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4 T_PRE_DCHR_78 R/W 11b PDR control loop pre-discharge time for half-bridge 7 and 8. Set as ratio of T_DON_DOFF_78 [5:0]
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2 PRE_CHR_INIT_78 R/W 01b PDR control loop initial pre-charge current setting for half-bridge 7 and 8.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0 PRE_DCHR_INIT_78 R/W 10b PDR control loop initial pre-discharge current setting for half-bridge 7 and 8.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

6.3.3.10 PDR_CTRL9 Register (Address = 33h) [Reset = 11h]

PDR_CTRL9 is shown in Figure 8-86 and described in Table 8-79.

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Control register to configure PDR Kp loop controller gain setting for half-bridges 1-4.

Figure 8-86 PDR_CTRL9 Register
7 6 5 4 3 2 1 0
EN_PDR_12 PDR_ERR_12 KP_PDR_12 EN_PDR_34 PDR_ERR_34 KP_PDR_34
R/W-0b R/W-0b R/W-01b R/W-0b R/W-0b R/W-01b
Table 8-79 PDR_CTRL9 Register Field Descriptions
Bit Field Type Reset Description
7 EN_PDR_12 R/W 0b Enable PDR loop control for half-bridge 1 and 2.
6 PDR_ERR_12 R/W 0b PDR loop error limit for half-bridge 1 and 2.
0b = 1-bit error
1b = Actual error
5-4 KP_PDR_12 R/W 01b PDR proportional controller gain setting for half-bridge 1 and 2.
00b = 1
01b = 2
10b = 3
11b = 4
3 EN_PDR_34 R/W 0b Enable PDR loop control for half-bridge 3 and 4.
2 PDR_ERR_34 R/W 0b PDR loop error limit for half-bridge 3 and 4.
0b = 1-bit error
1b = Actual error
1-0 KP_PDR_34 R/W 01b PDR proportional controller gain setting for half-bridge 3 and 4.
00b = 1
01b = 2
10b = 3
11b = 4

6.3.3.11 PDR_CTRL10 Register (Address = 34h) [Reset = 11h]

PDR_CTRL10 is shown in Figure 8-87 and described in Table 8-80.

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Control register to configure PDR Kp loop controller gain setting for half-bridges 5-8.

Figure 8-87 PDR_CTRL10 Register
7 6 5 4 3 2 1 0
EN_PDR_56 PDR_ERR_56 KP_PDR_56 EN_PDR_78 PDR_ERR_78 KP_PDR_78
R/W-0b R/W-0b R/W-01b R/W-0b R/W-0b R/W-01b
Table 8-80 PDR_CTRL10 Register Field Descriptions
Bit Field Type Reset Description
7 EN_PDR_56 R/W 0b Enable PDR loop control for half-bridge 5 and 6.
6 PDR_ERR_56 R/W 0b PDR loop error limit for half-bridge 5 and 6.
0b = 1-bit error
1b = Actual error
5-4 KP_PDR_56 R/W 01b PDR proportional controller gain setting for half-bridge 5 and 6.
00b = 1
01b = 2
10b = 3
11b = 4
3 EN_PDR_78 R/W 0b Enable PDR loop control for half-bridge 7 and 8.
2 PDR_ERR_78 R/W 0b PDR loop error limit for half-bridge 7 and 8.
0b = 1-bit error
1b = Actual error
1-0 KP_PDR_78 R/W 01b PDR proportional controller gain setting for half-bridge 7 and 8.
00b = 1
01b = 2
10b = 3
11b = 4

6.3.3.12 STC_CTRL1 Register (Address = 35h) [Reset = 23h]

STC_CTRL1 is shown in Figure 8-88 and described in Table 8-81.

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Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridges 1 and 2.

Figure 8-88 STC_CTRL1 Register
7 6 5 4 3 2 1 0
T_RISE_FALL_12 EN_STC_12 STC_ERR_12 KP_STC_12
R/W-0010b R/W-0b R/W-0b R/W-11b
Table 8-81 STC_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7-4 T_RISE_FALL_12 R/W 0010b Set switch-node VSH rise and fall time for half-bridge 1 and 2.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3 EN_STC_12 R/W 0b Enable STC loop control for half-bridge 1 and 2.
2 STC_ERR_12 R/W 0b STC loop error limit for half-bridge 1 and 2
0b = 1-bit error
1b = Actual error
1-0 KP_STC_12 R/W 11b STC proportional controller gain setting for half-bridge 1 and 2.
00b = 1
01b = 2
10b = 3
11b = 4

6.3.3.13 STC_CTRL2 Register (Address = 36h) [Reset = 23h]

STC_CTRL2 is shown in Figure 8-89 and described in Table 8-82.

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Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridges 3 and 4.

Figure 8-89 STC_CTRL2 Register
7 6 5 4 3 2 1 0
T_RISE_FALL_34 EN_STC_34 STC_ERR_34 KP_STC_34
R/W-0010b R/W-0b R/W-0b R/W-11b
Table 8-82 STC_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-4 T_RISE_FALL_34 R/W 0010b Set switch-node VSH rise and fall time for half-bridge 3 and 4.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3 EN_STC_34 R/W 0b Enable STC loop control for half-bridge 3 and 4.
2 STC_ERR_34 R/W 0b STC loop error limit for half-bridge 3 and 4.
0b = 1-bit error
1b = Actual error
1-0 KP_STC_34 R/W 11b STC proportional controller gain setting for half-bridge 3 and 4.
00b = 1
01b = 2
10b = 3
11b = 4

6.3.3.14 STC_CTRL3 Register (Address = 37h) [Reset = 23h]

STC_CTRL3 is shown in Figure 8-90 and described in Table 8-83.

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Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridges 5 and 6.

Figure 8-90 STC_CTRL3 Register
7 6 5 4 3 2 1 0
T_RISE_FALL_56 EN_STC_56 STC_ERR_56 KP_STC_56
R/W-0010b R/W-0b R/W-0b R/W-11b
Table 8-83 STC_CTRL3 Register Field Descriptions
Bit Field Type Reset Description
7-4 T_RISE_FALL_56 R/W 0010b Set switch-node VSH rise and fall time for half-bridge 5 and 6.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3 EN_STC_56 R/W 0b Enable STC loop control for half-bridge 5 and 6.
2 STC_ERR_56 R/W 0b STC loop error limit for half-bridge 5 and 6.
0b = 1-bit error
1b = Actual error
1-0 KP_STC_56 R/W 11b STC proportional controller gain setting for half-bridge 5 and 6.
00b = 1
01b = 2
10b = 3
11b = 4

6.3.3.15 STC_CTRL4 Register (Address = 38h) [Reset = 23h]

STC_CTRL4 is shown in Figure 8-91 and described in Table 8-84.

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Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridges 7 and 8.

Figure 8-91 STC_CTRL4 Register
7 6 5 4 3 2 1 0
T_RISE_FALL_78 EN_STC_78 STC_ERR_78 KP_STC_78
R/W-0010b R/W-0b R/W-0b R/W-11b
Table 8-84 STC_CTRL4 Register Field Descriptions
Bit Field Type Reset Description
7-4 T_RISE_FALL_78 R/W 0010b Set switch-node VSH rise and fall time for half-bridge 7 and 8.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3 EN_STC_78 R/W 0b Enable STC loop control for half-bridge 7 and 8.
2 STC_ERR_78 R/W 0b STC loop error limit for half-bridge 7 and 8.
0b = 1-bit error
1b = Actual error
1-0 KP_STC_78 R/W 11b STC proportional controller gain setting for half-bridge 7 and 8.
00b = 1
01b = 2
10b = 3
11b = 4

6.3.3.16 DCC_CTRL1 Register (Address = 39h) [Reset = 0h]

DCC_CTRL1 is shown in Figure 8-92 and described in Table 8-85.

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Control register to enable DCC loop and manual configuration for half-bridges 1-8.

Figure 8-92 DCC_CTRL1 Register
7 6 5 4 3 2 1 0
EN_DCC_12 EN_DCC_34 EN_DCC_56 EN_DCC_78 IDIR_MAN_12 IDIR_MAN_34 IDIR_MAN_56 IDIR_MAN_78
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 8-85 DCC_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7 EN_DCC_12 R/W 0b Enable duty cycle compensation for half-bridge 1 and 2.
6 EN_DCC_34 R/W 0b Enable duty cycle compensation for half-bridge 3 and 4.
5 EN_DCC_56 R/W 0b Enable duty cycle compensation for half-bridge 5 and 6.
4 EN_DCC_78 R/W 0b Enable duty cycle compensation for half-bridge 7 and 8.
3 IDIR_MAN_12 R/W 0b Current polarity detection mode for half-bridge 1 and 2.
0b = Automatic
1b = Manual (Set by HBx_HL)
2 IDIR_MAN_34 R/W 0b Current polarity detection mode for half-bridge 3 and 4.
0b = Automatic
1b = Manual (Set by HBx_HL)
1 IDIR_MAN_56 R/W 0b Current polarity detection mode for half-bridge 5 and 6.
0b = Automatic
1b = Manual (Set by HBx_HL)
0 IDIR_MAN_78 R/W 0b Current polarity detection mode for half-bridge 7 and 8.
0b = Automatic
1b = Manual (Set by HBx_HL)

6.3.3.17 PST_CTRL1 Register (Address = 3Ah) [Reset = Fh]

PST_CTRL1 is shown in Figure 8-93 and described in Table 8-86.

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Control register to configure max freewheeling current and post charge delay for half-bridges 1-8.

Figure 8-93 PST_CTRL1 Register
7 6 5 4 3 2 1 0
FW_MAX_12 FW_MAX_34 FW_MAX_56 FW_MAX_78 EN_PST_DLY_12 EN_PST_DLY_34 EN_PST_DLY_56 EN_PST_DLY_78
R/W-0b R/W-0b R/W-0b R/W-0b R/W-1b R/W-1b R/W-1b R/W-1b
Table 8-86 PST_CTRL1 Register Field Descriptions
Bit Field Type Reset Description
7 FW_MAX_12 R/W 0b Gate drive current used for freewheeling MOSFET for half-bridge 1 and 2.
0b = PRE_CHR_MAX_12 [1:0] 1b = 64 mA
6 FW_MAX_34 R/W 0b Gate drive current used for freewheeling MOSFET for half-bridge 3 and 4.
0b = PRE_CHR_MAX_34 [1:0] 1b = 64 mA
5 FW_MAX_56 R/W 0b Gate drive current used for freewheeling MOSFET for half-bridge 5 and 6.
0b = PRE_CHR_MAX_56 [1:0] 1b = 64 mA
4 FW_MAX_78 R/W 0b Gate drive current used for freewheeling MOSFET for half-bridge 7 and 8.
0b = PRE_CHR_MAX_78 [1:0] 1b = 64 mA
3 EN_PST_DLY_12 R/W 1b Enable post-charge time delay. Time delay is equal to T_DON_DOFF_12 - T_PRE_CHR_12.
2 EN_PST_DLY_34 R/W 1b Enable post-charge time delay. Time delay is equal to T_DON_DOFF_34 - T_PRE_CHR_34.
1 EN_PST_DLY_56 R/W 1b Enable post-charge time delay. Time delay is equal to T_DON_DOFF_56 - T_PRE_CHR_56.
0 EN_PST_DLY_78 R/W 1b Enable post-charge time delay. Time delay is equal to T_DON_DOFF_78 - T_PRE_CHR_78.

6.3.3.18 PST_CTRL2 Register (Address = 3Bh) [Reset = 55h]

PST_CTRL2 is shown in Figure 8-94 and described in Table 8-87.

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Control register to configure post charge Kp loop controller gain setting for half-bridges 1-8.

Figure 8-94 PST_CTRL2 Register
7 6 5 4 3 2 1 0
KP_PST_12 KP_PST_34 KP_PST_56 KP_PST_78
R/W-01b R/W-01b R/W-01b R/W-01b
Table 8-87 PST_CTRL2 Register Field Descriptions
Bit Field Type Reset Description
7-6 KP_PST_12 R/W 01b Post charge proportional control gain setting for half-bridges 1 and 2.
00b = Disabled
01b = 2
10b = 4
11b = 15
5-4 KP_PST_34 R/W 01b Post charge proportional control gain setting for half-bridges 3 and 4.
00b = Disabled
01b = 2
10b = 4
11b = 15
3-2 KP_PST_56 R/W 01b Post charge proportional control gain setting for half-bridges 5 and 6.
00b = Disabled
01b = 2
10b = 4
11b = 15
1-0 KP_PST_78 R/W 01b Post charge proportional control gain setting for half-bridges 7 and 8.
00b = Disabled
01b = 2
10b = 4
11b = 15